What parts of the DDR can I reserve using device tree without upsetting U-Boot?
I've been trying to build-time reserve a 64KiB memory region anywhere between 0xC0000000 & 0xDFFFFFFF for the Cortex-M4 core using a device tree reserved-memory node. I've tried 0xC0000000, 0xD0000000 & 0xDFFF0000 but each time U-Boot fails either during flash programming or when trying to boot the Linux kernel.
I've managed to kludge a reservation at 0xC0000000 by changing the root memory@c0000000 node to have "reg = <0xc0010000 0x3fff0000>;" after which I can read & write the 64KiB from the M4 without crashing the running Linux kernel and use it, for example, as additional M4 heap.
However this is icky. Ideally, I'd like the flexibility to assign it to the memory-region property in the &m4_rproc node and have rproc able to load data or code into it or use it for true zero-copy shared memory between the two domains. (Unlike the provided mechanism that uses DMA to move data between SRAM & DDR.)
I have searched the ST & community wikis to no avail for more detail. At this point I'm wondering if I'm going to have to reverse-engineer why U-Boot is objecting to reserved-memory nodes below 0xE0000000.
