How to enable 3 USB ports on STM32MP1

[PGE]

According to different STM32MP1 documentation such as STM32MP1-Peripheral-USB_Host_interface_USBH or STM32MP1-Peripheral-USB-On-The-Go-Full-and-HighSpeed-interface presentation there is two USB phy, one dual port HS phy and one single port FS phy.

In my understanding I should be able to enable 3 USB host port, two HS and one FS.

I am using the STM32CubeMX tool but I am unable to enable such 3 ports. I am able to enable two HS port but I am unable to enable OTG port. If I disable one HS port I am able to enable OTG port. So it seems STM32CubeMX allows to enable only two ports at the same time.

 

Is this an issue of STM32CubeMX or it's a real limitation of the chip ?

Note, I have tried with different package with the same results

 

Many thanks in advance for any help

[PatrickF]

Hello,

This is a limitation in CubeMX, I confirm you could really use three host ports (2 x high-speed + 1 x full-speed).

You have to edit the device tree manually for this case. see https://wiki.st.com/stm32mpu/wiki/OTG_device_tree_configuration#DT_configuration_example_as_full-speed_OTG-2C_with_micro-B_connector

Notice that OTG host HW/driver has some limitations which make it not recommended to be connected to an USB Hub.

[RMU]

Hi,

I had a similar problem with kernel 6.1.28, but I managed to solve it.I now can use all three USB ports ( 2xHS + OTG_FS )

I had the following message when connecting the board in peripheral mode :

dwc2 49000000.usb-otg: Failed to exit L1 sleep state in 200us

Patch : https://lore.kernel.org/lkml/[e-mail]/

 

From: Amelie Delaunay <[e-mail]>
To: Minas Harutyunyan <[e-mail]>,
	Felipe Balbi <[e-mail]>,
	Greg Kroah-Hartman <[e-mail]>
Cc: <[e-mail]>, <[e-mail]>,
	<[e-mail]>,
	Fabrice Gasnier <[e-mail]>,
	Amelie Delaunay <[e-mail]>
Subject: [PATCH 3/3] usb: dwc2: disable Link Power Management on STM32MP15 HS OTG
Date: Mon, 23 Nov 2020 10:01:14 +0100	[thread overview]
Message-ID: <[e-mail]> (raw)
In-Reply-To: <[e-mail]>

Link Power Management (LPM) on STM32MP15 OTG HS encounters instabilities
with some Host controllers. OTG core fails to exit L1 state in 200us:
"dwc2 49000000.usb-otg: Failed to exit L1 sleep state in 200us."
Then the device is still not enumerated.

To avoid this issue, disable Link Power Management on STM32MP15 HS OTG.

Signed-off-by: Amelie Delaunay <[e-mail]>
---
 drivers/usb/dwc2/params.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 9e5dd7f3f2f6..92df3d620f7d 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -194,6 +194,10 @@ static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
 	p->host_perio_tx_fifo_size = 256;
 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
+	p->lpm = false;
+	p->lpm_clock_gating = false;
+	p->besl = false;
+	p->hird_threshold_en = false;
 }
 
 const struct of_device_id dwc2_of_match_table[] = {
-- 
2.17.1

 

Here is a working device-tree allowing to use both USB in high-speed and OTG as full-speed:

 

/dts-v1/;

#include "stm32mp157c-odyssey-som.dtsi"

/ {
	model = "Seeed Studio Odyssey-STM32MP157C Board";
	compatible = "seeed,stm32mp157c-odyssey",
		 "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";

	aliases {
		ethernet0 = &ethernet0;
		serial0 = &uart4;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&dcmi {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&dcmi_pins_b>;
	pinctrl-1 = <&dcmi_sleep_pins_b>;
};

&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii-id";
	max-speed = <1000>;
	phy-handle = <&phy0>;
	assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>;
	assigned-clock-parents = <&rcc PLL4_P>;
	assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
	st,eth-clk-sel;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@7 { /* KSZ9031RN */
			reg = <7>;
			reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */
			reset-assert-us = <10000>;
			reset-deassert-us = <300>;
		};
	};
};

&i2c1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c1_pins_a>;
	pinctrl-1 = <&i2c1_sleep_pins_a>;
	i2c-scl-rising-time-ns = <100>;
	i2c-scl-falling-time-ns = <7>;
	status = "okay";
	/delete-property/dmas;
	/delete-property/dma-names;
};

&sdmmc1 {
	pinctrl-names = "default", "opendrain", "sleep";
	pinctrl-0 = <&sdmmc1_b4_pins_a>;
	pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
	pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
	cd-gpios = <&gpioi 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
	disable-wp;
	st,neg-edge;
	bus-width = <4>;
	vmmc-supply = <&v3v3>;
	status = "okay";
};

&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins_a>;
	/delete-property/dmas;
	/delete-property/dma-names;
	status = "okay";
};

&usbotg_hs {
	compatible = "st,stm32mp15-fsotg", "snps,dwc2";
	pinctrl-names = "default";
	pinctrl-0 = <&usbotg_fs_dp_dm_pins_a>;
	dr_mode = "device";
	status = "okay";
};

&pinctrl {
	usbotg_hs_pins_b: usbotg-hs-1 {
		pins {
			pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* OTG_ID */
		};
	};
};

&usbphyc {
	status = "okay";
};


&usbphyc_port0 {
	st,tune-hs-dc-level = <2>;
	st,enable-fs-rftime-tuning;
	st,enable-hs-rftime-reduction;
	st,trim-hs-current = <15>;
	st,trim-hs-impedance = <1>;
	st,tune-squelch-level = <3>;
	st,tune-hs-rx-offset = <2>;
	st,no-lsfs-sc;
	connector {
		compatible = "usb-a-connector";
		vbus-supply = <&vbus_sw>;
	};
};


&usbphyc_port1 {
	st,tune-hs-dc-level = <2>;
	st,enable-fs-rftime-tuning;
	st,enable-hs-rftime-reduction;
	st,trim-hs-current = <15>;
	st,trim-hs-impedance = <1>;
	st,tune-squelch-level = <3>;
	st,tune-hs-rx-offset = <2>;
	st,no-lsfs-sc;
	connector {
		compatible = "usb-a-connector";
		vbus-supply = <&vbus_sw>;
	};
};

&vdd_usb {
	regulator-always-on;
};

&vdda {
	regulator-always-on;
};

&usbh_ohci {
	phys = <&usbphyc_port0> ;
	phy-names="usb2-phy";
	status = "disabled";
};

&usbh_ehci{
	phys = <&usbphyc_port0>, <&usbphyc_port1 1>;
	status = "okay";
};

 

 

[PGE]

Ok many thanks for your clear reply

Any other known limitation ? Is there any documentation with all known limitation / issue ?

[PatrickF]

See ES0438: STM32MP151x/3x/7x device limitations

See also https://wiki.st.com/stm32mpu/wiki/STM32MP15_ecosystem_release_note

[PGE]

@PatrickF​ According to your link above default IOs for USB OTG in full-speed mode are PA11 and PA12. These are general purpose IOs, are they powered by VDD or VDD_USB ? As USB is 3.3V signals does-it work well also with 1.8V VDD powered STM32MP157 ?

Thanks in advance for clarification

[PatrickF]

PA11 and PA12 are specific IOs and supplied by VDD_USB (3.3V typ.) when used as OTG_FS data pins, VDD otherwise.

No issue regarding VDD=1.8V