STM32H503 – ADC trigger shifting from OFF midpoint at duty > 50% in center-aligned complementary PWM

[PRAKKU12]

Subject: STM32H503 – ADC trigger shifting from OFF midpoint at duty > 50% in center-aligned complementary PWM

Hi all,

I am working on a DC-DC converter using the STM32H503RBT6. I have configured TIM1 to generate:

• Two complementary PWM pairs

• 180° phase shift between the two PWM channels

• Center-aligned mode 1

Additionally, I am generating:

• Two ADC trigger events (using TRGO/TRGO2)

• These triggers are also intended to be 180° phase-shifted

• Trigger frequency is the same as the PWM frequency

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:direct_hit: Requirement

For both PWM phases, the ADC trigger should occur:

At the midpoint of the OFF time of the high-side (top) switch

This is required for accurate current sensing.

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:gear: Current Implementation

• Timer: TIM1 in center-aligned mode

• Complementary PWM enabled

• Interleaving achieved using PWM mode 1 and PWM mode 2

• Two trigger sources:

  • One near CNT = 0

  • One near CNT = ARR

• ADC is triggered using TIM1 TRGO and TRGO2

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:exclamation_mark: Problem

• For duty cycle up to 50%, both triggers correctly occur at the midpoint of the OFF time

• When duty cycle exceeds 50%, one of the trigger points shifts:

  • From the OFF-time midpoint

  • Into the ON-time region of the PWM

This causes incorrect ADC sampling.

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:magnifying_glass_tilted_left: Observation

• The issue becomes more prominent at higher duty cycles

• Dead time (previously ~500 ns) also affects the effective OFF window

• It appears that the trigger point is no longer aligned with the OFF region when duty increases

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:question_mark: Question

• Why does the trigger shift into the ON region when duty > 50% in center-aligned mode?

• Is this due to the way compare events behave during up/down counting?

• What is the correct method to ensure:

  • Fixed 180° phase shift between triggers

  • AND ADC sampling always at the midpoint of the OFF time?

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:paperclip: Additional Info

I have attached:

• TIM1 PWM configuration code

• ADC configuration

• Interrupt/duty update logic

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Any guidance or recommended approach would be very helpful.

Thanks in advance!

[waclawek.jan]

Please don't AI generate the questions to forum. Or at least have the decency to hand-edit it to be humanly readable.

How do you know where is the ADC trigger point?

What is the TIM1 period?

JW

[PRAKKU12]

I have attached all the configuration files of my timer as well as adc and also interrupt configuration file where iam updating duty.
Anyway my TIM1 period is 833 and system clock is 250MHz and its a center aligned PWM.i have checked the trigger source in scope with respect to PWM.iam triggering adc one at close to 0 value and the other one close to ARR.

[waclawek.jan]

I don't use Cube/HAL/CubeMX so don't uderstand that code.

So, you say, that the output of channels you are using for ADC triggering is not where you expect them to be? In that case, it's not related to ADC at all, is it? It's a purely TIM-related issue, then.

Can you please read out and post content of TIM registers in the "working" and in the "non-working" state, together with oscilloscope screenshots for the respective states?

JW