STM32H7A3ZIT6 Half Flash Bricked/Corrupted

[DReis.2]

Hi,

I'm facing this weird behavior with many STM32H7A3ZIT6 parts, where after we flash our Firmware, the MCU do not work and when we read the flash content, we can notice that one flash bank (1MB) is either corrupted with random data or erased. Sometimes we see Bank 0 in this state, other times Bank1.

When this happens we check using STM32CubeProgrammer, the option bytes are normal (no read or write protection is checked), and more interestingly is that STLink returns a weird Flash Size Value

First Bank with random data

 

Second Bank is normal (has valid code)

 

Invalid Flash Size (After mas erased this reads Ok, but fails again after FW is flashed)

 

While flashing the code, the STM32CubeProgrammer returns success, even though we can't read one of the banks properly.

I've also tried flashing using STM32CubeIDE with OpenOCD but the problem persists.

 

Below is the image of a Chip we are using

 

Option Bytes

 

I could not come to any conclusion so far, and I'm afraid the MCUs with this issue are bricked forever.

Has anyone faced such a problem before?

In the FW we don't do any access to write the internal Flash also we don't change any option byte. The MCU is running at 280MHz (we also tested with 120MHz). Data and Instruction Cache are enabled

[Tesla DeLorean]

Strap BOOT0 HIGH, and fully/completely power cycle the core several times, to ensure your code is not run.

The check with STM32 Cube Programmer directly

Check what you're doing with LDO / SMPS settings, and VOS settings in SystemClock_Config()

[DReis.2]

@Community member​ When the MCU enters this state, and I remove all power supply and wait, I'm able to write the entire flash, but eventually the problem appears again after running for awhile

The MCU part I am using is LDO only, configured with VOS0 for 280MHz

Below is the SystemClock_Config() used.

void SystemClock_Config(void) {
	RCC_OscInitTypeDef RCC_OscInitStruct = {
		0
	};
	RCC_ClkInitTypeDef RCC_ClkInitStruct = {
		0
	};
 
	/** Supply configuration update enable
	 */
	HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
	/** Configure the main internal regulator output voltage
	 */
	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
 
	while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {
	}
	/** Configure LSE Drive Capability
	 */
	HAL_PWR_EnableBkUpAccess();
	__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);
 
	/** Macro to configure the PLL clock source
	 */
	__HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSI);
 
	/** Initializes the RCC Oscillators according to the specified parameters
	 * in the RCC_OscInitTypeDef structure.
	 */
	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI
			| RCC_OSCILLATORTYPE_LSE;
	RCC_OscInitStruct.LSEState = RCC_LSE_ON;
	RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
	RCC_OscInitStruct.HSIState = RCC_HSI_DIV1;
	RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
	RCC_OscInitStruct.LSIState = RCC_LSI_ON;
	RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
	RCC_OscInitStruct.PLL.PLLM = 4;
	RCC_OscInitStruct.PLL.PLLN = 35;
	RCC_OscInitStruct.PLL.PLLP = 2;
	RCC_OscInitStruct.PLL.PLLQ = 2;
	RCC_OscInitStruct.PLL.PLLR = 2;
	RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
	RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
	RCC_OscInitStruct.PLL.PLLFRACN = 0;
	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
		Error_Handler();
	}
	/** Initializes the CPU, AHB and APB buses clocks
	 */
	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
			| RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
	RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
	RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
	RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
	RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
	RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
	RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
 
	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) {
		Error_Handler();
	}
	/*
	 Note : The activation of the I/O Compensation Cell is recommended with communication interfaces
	 (GPIO, SPI, FMC, OSPI ...) when operating at high frequencies(please refer to product datasheet)
	 The I/O Compensation Cell activation procedure requires :
	 - The activation of the CSI clock
	 - The activation of the SYSCFG clock
	 - Enabling the I/O Compensation Cell : setting bit[0] of register SYSCFG_CCCSR
 
	 To do this please uncomment the following code
	 */
 
	__HAL_RCC_CSI_ENABLE();
 
	__HAL_RCC_SYSCFG_CLK_ENABLE();
 
	HAL_EnableCompensationCell();
	PeriphCommonClock_Config();
}