External interrupt flags latching behaviour?

[martonmiklos]

Posted on May 10, 2017 at 10:46

I am working on a code which utilizes External interrupts on the PORT B.

STM8AF5286 is used with the Cosmic compiler.

I have not found any information about how the interrupt flags are handled internally and knowing their behavior would be important for my project.

On the logic analyzer capture below you can see that the pulse on the PORTB 0 is 1.26 us, which triggers two interrupts. which first and last instruction toggles the pin captured with the ISR channel.

The PB_ODR read is performed in the next instruction after the ISR pin low to high transition. 

In both routines it reads zero from the PORT B.

Is there any way to clear the pending interrupt flag in the serviced interrupt routine?

#external-interrupt #interrupts

Posted on February 25, 2018 at 22:27

I got a similar problem. I noticed that when there is a transition of an external interrupt pin while in the interrupt routine servicing this interrupt, immediately after you finish the interrupt routine it will fire another one. The only way to avoid this is to immediately disable EXTI interrupt on that particular pin inside the interrupt service routine.

[Pavan Kumar Ogirala]

Posted on May 08, 2018 at 12:33

This occurs due sensitivity selection parameter configuration for external interrupts. Most of stm8 micro controllers provide the following options

00: Falling edge and low level

01: Rising edge only

10: Falling edge only

11: Rising and falling edge

The default being 00 you might be seeing a repeated ISR's if you are not configuring the sensitivity to a value different than 00 (based on the application).