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Visitor II
June 10, 2013
Question

HSI Power Down

  • June 10, 2013
  • 2 replies
  • 956 views
Posted on June 10, 2013 at 16:48

Hello everybody,

I'm programming a STM8L152C6 on the STM8L-discovery. Wanting to improve the consomption I tri to power down the HSI. For that I use the instruction

  // Clock source

  CLK_LSICmd(ENABLE);

  CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_LSI);

  while(((CLK->ICKCR) && CLK_ICKCR_LSIRDY)==0);

  CLK_SYSCLKSourceSwitchCmd(ENABLE);

  CLK_HSICmd(DISABLE);

  CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_1);

What seems to work for some people according to the topics I read on this site. I'm switching the clock source perfectly and the HSION bit in the CLK_ICKCR is 0. But the HSIRDY in the CLK_ICKCR is steel to 1 and the HSIPD in the CLK_REGCSR is to 0. I'm not using any peripheral for the moment.

Am I doing something wrong? What could avoid the HSI to turn down?

I hope someone can help me. Thank you very much.

#stm8l-hsi
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    2 replies

    Visitor II
    November 1, 2013
    Posted on November 01, 2013 at 08:18 I am having the same issue with STM8S003F3. Here's what I do in main():

    CLK->SWCR = CLK_SWCR_SWEN; 
    // enable clock switching
    CLK->SWR = 0xB4; 
    // set target clock source to HSE
    while
    ( CLK->SWCR & CLK_SWCR_SWBSY ); 
    // wait for clock switch
    CLK->CKDIVR = 0x00; 
    // sys clock divider /1
    CLK->PCKENR1 = CLK_PCKENR1_UART1 | CLK_PCKENR1_I2C; 
    // enable UART, I2C clocks
    CLK->PCKENR2 = 0x00; 
    // disable ADC, AWU clocks
    CLK->ICKR = 0x00; 
    // disable internal RC oscillators

    Using STVD debugger over SWIM, looking at internal registers. After last instruction that should disable HSI, theHSIRDY bit remains set, even thoughHSIEN is clear. As a sanity check when I enable HSI as a clock out source, the HSIEN cannot be cleared as expected. How to kill the HSI for good?
    Visitor II
    November 1, 2013
    Posted on November 01, 2013 at 15:37

    It looks like the SWIM module forces HSI on.  Check out ''STM8 SWIM communication protocol and debug module''  UM0470.  Figure 4 shows the HSI forced on as part of the SWIM entry sequence.  You'll probably have to verify the death of the HSI via current measurement or some other non-SWIM means.

    jdf