Interrupt at DIVW and DIV

[wolfgang239955_stm1_st]

Posted on September 19, 2013 at 11:21

Hi,

today I have a very special question:

I read in the programming manual, that the instructions DIV an DIVW are interruptible.

What exactly happens, when an interrupt occurs while calculating is active 

- with the registers (A, X, Y) and

- how does calculating continue after IRET???

Who can answer?

TIA,

WoRo

#divw #div

[fggnrc2]

Posted on September 26, 2013 at 16:50

Hello WoRo!

I don't know how STM8 core implements DIV/DIVW instructions.

STM8 errata documents provide some insight, as there is always an ''Unexpected DIV/DIVW instruction in ISR'' sub-section.

This error happens when an interrupt executes a DIV/DIVW instruction and another event interrupts the IRET instruction.

It seems that unused CC bits play some role in DIV/DIVW execution.

In my opinion, a dedicated hardware unit processes DIV/DIVW instructions and when its result is ready, the involved registers are updated. This update may be forced by one of these unused bits (which are usually null), but only the STM8 core designers know what happens.

I think that ISRs should avoid these instructions, but it may be too much conservative...

EtaPhi

[fggnrc2]

Posted on September 26, 2013 at 18:36

I unsuccessfully tried to exercise IRET instruction by simulating an interrupt stack frame.

Whatever the CC value to restore is, the output is the same: no unexpected X or Y register value.

It seems that bit 6 of CC, which is undefined, has no effect on IRET execution.

For this reason, I suppose that DIV/DIVW instructions use shadow registers, which user code can't access, and a flip/flop which is hidden to the user too.

Sorry, it seems that there is no answer to your question.

Regards,

EtaPhi