STM8 Basic Timer1 function

[jpollock]

Posted on March 26, 2013 at 05:48

I cant seem to decipher the TIM1 registers to get a basic timer function similar to TIM2 or TIM4.  Count UP and interrupt only if you reach the auto-reload period. In my application I reset the counter to 0 before the period is reached so a timer interrupt is a fault of sorts. TIM1 generates an interrupt when I set the counter to 0. Is there a way to inhibit that portion of the update interrupt?  Can a compare be used without and output?

currently I use the standard library provided and the intent below was to have the timers operate equally:

  TIM1_TimeBaseInit(0x0020, TIM1_COUNTERMODE_UP, 0x00B4, 1 );

  /* Enable TIM1 IT UPDATE */

  TIM1_ITConfig( TIM1_IT_UPDATE, ENABLE);

  /* Enable TIM1 */

//  TIM1_Cmd(ENABLE);

 

//  TIM2_DeInit();

  /* Time base configuration */

  TIM2_TimeBaseInit(TIM2_PRESCALER_64, 0x00B4 );

  /* Enable TIM2 IT UPDATE */

  TIM2_ITConfig(TIM2_IT_UPDATE, ENABLE);

  /* Enable TIM2 */

 // TIM2_Cmd(ENABLE);

 

 // TIM4_DeInit();

  /* Time base configuration */

  TIM4_TimeBaseInit(TIM4_PRESCALER_64, 0xB4 );

  /* Enable TIM4 IT UPDATE */

  TIM4_ITConfig(TIM4_IT_UPDATE, ENABLE);

Thanks John

#tim1-stm8s

[jpollock]

Posted on March 26, 2013 at 19:46

I've found it impossible to directly write to the counter register with software without generating an interrupt. However I can reset the counter to 0 using the following:

     TIM1->CR1 |= (uint8_t)(TIM1_CR1_UDIS);

     TIM1->EGR |= (uint8_t)(TIM1_EGR_UG);

     TIM1->CR1 &= (uint8_t)(~TIM1_CR1_UDIS); 

Turn OFF the setting of the UIF flag with UDIS then reset the counters (and other shadow registers) and then re-enable the UIF flag so that if the timer goes OFF you will get the overflow/underflow interrupt.

The manual suggests that just setting the URS bit of the CR1 register will enable ONLY the over/underflow interrupt but that didn't seems to work. I still got interruopts when I write a 0 to the counter.

John