STM8S and EXTI and Continuous Interrupts

[Workalot]

Posted on January 24, 2012 at 08:25

MCU: STM8S105C6

Port: GPIOB

Bit: 2 

GPIOB:2 is the only pin/bit set up for external interrupt, yet regardless of any edge sensitivity setting in EXTI_CR1, once an interrupt is invoked it is continuously invoked while ever the input pin is low. As the STM8S appears to have has no register for clearing an interrupt flag, what mechanism am I missing?   

Other posts have discussed similar experiences but have not been conclusive in an answer.

The project manipulates registers directly rather than through ST's FWLIB. 

Workalot

[wolfgang239955_stm1_st]

Posted on January 24, 2012 at 09:36

Hi,

as you give us little information, I can only try.

In the Reference Manual of the STM8S Family I found on page 89 the chapter maskable interrupt sources and there especially

External interrupts

.....

When several input pins connected to the same interrupt line are selected

simultaneously, they are logically ORed.

When external level-triggered interrupts are latched, if the given level is still present at

the end of the interrupt routine, the interrupt remains activated except if it has been

inactivated in the routine.

Are you using level-triggered interrupt? If not, give us more information.

Regards,

WoRo

[Workalot]

Posted on January 24, 2012 at 10:42

Hello WoRo - thanks for your quick response. This is in return, a quick response. I should my tomorrow prepare a minimal project demonstrating the problem and post it.

But for now...

While EXTI sensitivity is port wide (that is across all bits of that port), if we have...

GPIOB_CR2 = 0x04; // Only bit 2 gated through to the ITC (Fig 21, page 100)

EXTI_CR1 = 0x08; // PBIS = b10 = falling edge

Is this not enough that only bit2 can cause an EXTI interrupt, and only do so on a hi to lo edge?

regards - workalot

[wolfgang239955_stm1_st]

Posted on January 24, 2012 at 13:52

Hi,

Did you consider the notice at EXTI_CR1?

Bits 3:2 PBIS[1:0]:

Port B external interrupt sensitivity bits

 

These bits can only be written when

I1 and I0 in the CCR register are both set to 1 (level 3).

 

 

Otherwise you may keep the default value 00: falling and low level

 

 

Regards,

WoRo

[Workalot]

Posted on January 25, 2012 at 23:06

Have done a minimal project based on STVD + Cosmic which demonstrates a contradiction to my earlier claim. Have included the files should anyone else need confirmation that EXTI works appropriately.

workalot

________________

Attachments :

stm8_interrupt_vector.c : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HzFN&d=%2Fa%2F0X0000000bKq%2Fn92XdKa160_J6X9DKYETk0WX7yp1AHPpDmUBJRKlhwM&asPdf=false

[Workalot]

Posted on January 25, 2012 at 23:08

The second of two files.

________________

Attachments :

exti_test.c : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HzMd&d=%2Fa%2F0X0000000bKp%2FdfCFdLkSiEN9m.ZKcXArjNqgbbo2ZhiajJ5KuiWedNc&asPdf=false

[pok-on]

Posted on March 07, 2014 at 09:16

Thank You,

Your post saved a lot of time to me. Thumbs up!