STM8S003F3 VIH and VIL levels

[martonmiklos]

Hello all,

I have an application based on the STM8S003F3 where invalid logic levels could appear on the UART RX line. (By design due to the ground offsets in a bigger system.) In some cases the UART misinterprets bytes mainly when the low level of the 0 bits is around 2.2V

In the DS7147 page 66 section 9.3.6 the following is present:

 

My application uses 5V VDD, so if I calculate right the VIHmin is 3.5V and the VILmax is 1.5 V in my case.

And in the following page there is a graph which is the following:

If I read it right the VIL is ~2.2V and the VIH is ~2.9V.

 

Which is the correct one?

[Max]

What is guarantied is what is in the table.

It corresponds to what is tested in production.

This kind of specification is kind of standard for CMOS digital inputs.

You should design your application using these values

The graph shows the values measured on one device (typical)

It provides information about temperature and supply voltage impact.

As you can see, it also gives you an idea about the design margin taken for these parameters...