STM8S103F3P6 slave SPI device with multiple CS

[ManuelGomez_Opt]

Hi,

 

We are trying to solve some problems regarding our SPI bus (bus stability, due to multiple branches in noisy environments) and reduce costs by eliminating a SPI sensor and make our STM8 to read a NTC. We would like the system to answer as the old SPI sensor, so we want to connect its CS to the STM8. The STM8 already had its own CS, so now it has two CS pins and we need it to answer to both of them. Is there a way to make this work?

 

Thanks in advance!

 

EDIT:

Attached you can find the schematic diagram of what I am trying to do. Basically we had a branched SPI bus (the master device can host up to 4 slave modules, each one has again a division of the SPI bus in two branches). We are eliminating the second branching, so there is only four branches with no extra division. The STM8 now has to read the NTC, extract the temperature and answer to the commands that were meant to be sent to the old temp sensor. We are trying to implement this in order not to change the FW in old master devices, so the new modules can be compatible with old host devices without upgrading them.

[Peter BENSCH]

Welcome @ManuelGomez_Opt, to the community!

Can you describe it in such a way that it can be understood?

Perhaps add extracts from the schematics, i.e. before and how it should look afterwards, because a drawing says more, rather than long explanations?

Regards
/Peter

[ManuelGomez_Opt]

Hi Peter,

I modified the original post in order to attach the diagram of what I am trying to do.

Regards,

Manuel

[Peter BENSCH]

As far as I can see, CS_1 previously selected the temperature sensor so that you could read its temperature, right?

Now you want to signal to the STM8 instead that it performs a temperature measurement with the NTC when CS_1 is active?

Well, this is relatively easy to do by using the software NSS management with SSM=1 (see RM0016, section 20.3). In this case, the SPI module is not controlled with the hardware NSS pin, but via the bit SSI (SPI_CR2). Now you only have to realise a logic that e.g:

• reads in the two signals CS_0 and CS_1 via one GPIO each,
• evaluates that only one of these signals may be active, otherwise the request is simply ignored,
• depending on the result of this evaluation, places the corresponding data in the SPI register and
• sets the bit SSI=0 for transmission, then SSI=1 again

This is only a suggestion, of course you can still intercept errors if, for example, the second CS is subsequently activated although the previously started SPI action of the first CS has not yet been completed.

Hope that helps?

Regards
/Peter