PCB layout for oscillator - separated GND plane confusion

[freeflyer]

I am designing a 4 layer PCB which uses an STM32L433 and working on the layout for the LSE and HSE crystals. 

I referred to the application note AN2867 for guidance, but I am confused by the isolated ground plane underneath the crystals as shown in Figure 14...

https://www.st.com/resource/en/application_note/an2867-guidelines-for-oscillator-design-on-stm8afals-and-stm32-mcusmpus-stmicroelectronics.pdf

 

1. How is the isolated ground plane supposed to be connected to the ground net ?

2. Do all inner layers need an isolated ground plane ?

 

At the moment, the isolated ground plane is only on inner layer 1 and its ground connection is made by the vias on the guard rail to inner layer 2.

 

Below are screenshots of the current implementation.

 

 

The screenshot below shows the top layer (signals in red) and inner 1 layer (ground in green)....

 

 

The screenshot below shows the top layer (signals in red) and inner 2 layer (ground in orange)....

The screenshot below shows the top layer (signals in red) and bottom layer (signals in blue)....

 

 

 

 

[freeflyer]

I have modified the design as shown in the screenshots below.  The modifications include:

• Isolated GND plane connected to main GND plane on inner layer 1
• Extended isolated GND plane to go under the STM32 pins
• Reduced via spacing on guard rail
• Removed isolated GND plane under on inner layer 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[Mikk Leini]

This is weird now. Didn't see you have ground poured on bottom layer in the first post. If you have ground poured all over the bottom layer then oscillator circuit is also part of it through the guard ring vias and isolation is not effective. But if you also isolate bottom layer ground, then another thing requires attention: narrow ground connection joint (which is roughly the width of a via on your middle layers) can cause other issues like extra impedance to your oscillator signals. It would be safer to leave it wider as I drew - e.g. the width of the oscillator pins.

To keep it simple - if you do not have high switching currents, high (RF) frequency sources/reception or sensitive analog circuits on the PCB or on oscillator side of the PCB (and it looks like that) then you can use single solid ground plane on bottom and middle layers. Without knowing all the details about your design, it feels less risky than creating complex issues. Don't bother with the app note too much - that full isolation is most likely for tightly packed PCBs with high-speed buses and advanced cases. Just leave the guard ring in place and leave clearance for crystals that others have mentioned. And don't cut that invisible ground return current path from oscillators and their load caps to MCU VSS pins with any other trace.

First versions always have some issue. Better plan multiple iterations of prototypes and make EMC pre-compliance testing to iron out issues.

PS.
Pins 63-64 supply decoupling capacitor routing looks good, but pin 12-13 is still bad (there is none). If you don't want to move oscillators further, then use bottom side for capacitor.

PPS.

Oscillators load capacitors and guard rings are connected on the top layer. I am not sure it's the best design. Maybe you should have separate ground via(s) for capacitors going into middle/bottom layers. You may squeeze that separate via(s) between capacitors and oscillator.

[freeflyer]

Thanks Mikk

There is no ground pour on the bottom layer (blue)?

Ground pour is only on inner layer 1 (green) and inner layer 2 (orange).

Are you referring to inner layer 2, where I removed the isolated island under the crystal ?

The board is compact (~60mm x ~32mm) and is fitted with buck-boost converters (for 3.3V and 5V rails), a class D audio amplifier (PWM) and a bluetooth audio receiver.
 
Thanks for pointing out the missing cap on pins 12 (VSSA) and 13 (VDDA).  This was missed because originally I used the STM32 DAC so used caps and a filter for VDDA (pin 13)...

 

 

 
But now I am not using any analogue functions (e.g. DAC, ADC) so I just connected pin 13 directly to +3.3V.  I have now added a 100nF cap between 12 (VSSA) and 13 (VDDA), is this acceptable ?

I dont understand some of your comments, could you please elaborate ?

You said...

"But if you also isolate bottom layer ground, then another thing requires attention: narrow ground connection joint (which is roughly the width of a via on your middle layers) can cause other issues like extra impedance to your oscillator signals"

Are you referring to this ground track highlighted in red...

I don't understand what you are saying, is the track too thin ?

 

You said...

"Oscillators load capacitors and guard rings are connected on the top layer. I am not sure it's the best design. Maybe you should have separate ground via(s) for capacitors going into middle/bottom layers. You may squeeze that separate via(s) between capacitors and oscillator."

Are you referring to the tracks highlighted in green...

 

Are you saying to give the cap ground an independent via, rather than connecting to the via on the guard rail ?

 

Below is my latest layout...

 

 

 

 

[Mikk Leini]

Hi @freeflyer . My bad, I thought the orange layer is the bottom layer as it was the last image, but you're right, it's one of the inner layers. However the point still remains - it still connects the grounds together and you don't have effective isolation.

Now to my comments. Questionable area is the narrow ground bottleneck that you marked and I mark here with red circle. I also drew estimated ground return currents with blue. That narrow passage (on multiple layers) could have extra impedance on the AC signals compared to a wider ground plane. I am not RF expert so I cannot tell how much. Beside that there are two oscillator ground currents mixed together on that narrow trace. Overall this narrow  trace is unnecessary risk. You don't win anything from it.

If I must use isolation, I would personally take a safe side and make it wider:

Regardless of the width of the ground trace, you can still have other disturbing ground currents, because MCU ground pin is on the other edge of the chip. Can't solve that.

 

You spotted the comment about guard ring and capacitors correctly. Suggestion is to provide separate ground current path for load capacitors so in case the guard ring shunts a stray current into ground, it has less effect on your oscillator circuit.

Ideally the guard ring should have low impedance/resistance path to the source in order for this small via change to have effect. But if it goes into the same (semi-)isolated ground plane as your signals, then I suspect that ground isolation starts to play negative effect here because that stray current passes the same ground connection as you oscillator signals. Unfortunately I don't have practical experience with such combined solution, maybe somebody else can comment it.

Yet, if you have solid ground plane, then guard ring stray currents are more likely to find shorter way back to their origin.

Considering all the complications with the isolation solution and negligible gain, I still recommend to make your life easier and use solid ground plane for MCU and oscillator. If you keep your switching regulators away and design them according to their design guidelines, then they don't trouble oscillators. If it's fully integrated D-class amplifier then it's not an issue either. Just make sure to provide its power (positive and negative) from your supply through shortest path (away from MCU) because there's a lot of switching current. Bluetooth - depends if it's a module or chip, but I'm sure you'll find it's app note also :)

Good luck!

Thanks for sharing this! From my experience, the isolated ground under the crystal is mainly to keep the oscillator area noise-free. It should still connect to the MCU’s ground at one point, ideally the nearest GND pin. Only the area under/around the crystal needs isolation, and all components should be as close as possible to the MCU pins. Avoid placing other traces or caps in that isolated area.