PCB layout for oscillator - separated GND plane confusion

[freeflyer]

I am designing a 4 layer PCB which uses an STM32L433 and working on the layout for the LSE and HSE crystals. 

I referred to the application note AN2867 for guidance, but I am confused by the isolated ground plane underneath the crystals as shown in Figure 14...

https://www.st.com/resource/en/application_note/an2867-guidelines-for-oscillator-design-on-stm8afals-and-stm32-mcusmpus-stmicroelectronics.pdf

 

1. How is the isolated ground plane supposed to be connected to the ground net ?

2. Do all inner layers need an isolated ground plane ?

 

At the moment, the isolated ground plane is only on inner layer 1 and its ground connection is made by the vias on the guard rail to inner layer 2.

 

Below are screenshots of the current implementation.

 

 

The screenshot below shows the top layer (signals in red) and inner 1 layer (ground in green)....

 

 

The screenshot below shows the top layer (signals in red) and inner 2 layer (ground in orange)....

The screenshot below shows the top layer (signals in red) and bottom layer (signals in blue)....

 

 

 

 

[Mikk Leini]

Technically you should connect the oscillator circuit ground connection close to the current source (MCU Xtal out pin) to have smallest possible current loop, but the closest MCU ground pin is not near Xtal pins, it's many pins away and that's probably a power ground pin (VSS). So not very ideal solution.

Well, it's only personal advice, but the way how I have interpreted the isolation requirement is that the area around and below oscillator circuit should be isolated from noise. So no other circuit ground currents should flow through that part of the circuit. It can be achieved like application note says - leave a gap with main ground, but that creates other issues. Yet if you manage to keep oscillator area noise free then you can use same solid ground plane for MCU and oscillator. You just need to judge based on the rest of the design. 

I agree—keeping the oscillator area noise-free is the key. Even if the closest GND pin isn’t near the crystal, isolating that area from other currents and carefully connecting it at a single point works well. A solid ground plane can still be used as long as you minimize interference in the oscillator region.

[AScha.3]

> 1. How is the isolated ground plane supposed to be connected to the ground net ?

1. Always it has to be connected to GND !

2. deeper sense of the isolated/separated area in gnd plane is: to avoid any current or voltage spikes disturbing the small analog signal at the crystal.

But this has to be connected to ground (chip ground), perfect if there is a "gnd" pin only for this - but if you have a package without so many gnd pins, use the closest/shortest next gnd pin to connect the crystal-gnd-area;

or if no pin close , just connect to gnd plane at/under cpu.

see from an2867: i made green arrow

 

 

> 2. Do all inner layers need an isolated ground plane ? no. Just at the crystal to avoid any stray in.

3. Dont connect the cap here - you couple the noise on 3v3 to the crystal-gnd , thats much worse than anything else !  Even no separate ground area and just a continuous gnd  plane would be better !

Nothing has to have any contact to this small ground area, except in one point at/close the cpu !!!!

[gbm]

From my experience: in order for LSI to oscillate on STM32L4, do not place ANY plane under it and avoid PCB traces running in parallel to its connections on the bottom side.

Also, the LSI and HSI traces should go through capacitors to the crystals (so put capacitors closer to MCU than the crystals.

[LCE]

The GND "isolation" definitely only refers to the outer layer where the crystal is placed, so that there is a "guard ring" around the crystal, as the picture also says.

As the others say, it would be nice to connect this guard ring only to the MCU's internal oscillator's GND pin, but too often it's simply not possible.

I'd say where the crystal caps are exactly placed doesn't matter, as long as all components are as close as possible to the MCU pins.

[freeflyer]

Thanks all

I have made the following modifications:

• Added isolated plane under the crystals on inner layer 2 (it was previously only isolated on inner layer 1). Note that both inner layer 1 and 2 are ground planes (inner layer 1 is continous ground plane, inner layer 2 has some power tracks within the ground plane)

• Connected isolated ground plane to pin 12 (GND) of STM32
  • Pin 12 is VSSA (analogue ground), will this be a problem ?
  • The STM32L433 only has a single ground pin (18)

• Disconnected isolated ground plane from the decoupling capacitor ground

And as before, no tracks run under the crystals

 

 

 

 

 

 

 

 

 

 

 

 

I have designed a few boards using this STM32 device and did not use isolated planes under the crystals or a gaurd rail, but it still worked.  Even the Nucleo development board does not use a guard rail.

 

So should I continue with these isolated planes and guard rail or is there a risk it could cause issues ? 

 

I dont know whether I should just design it the way I have previously, I would be furious if I spent a few hundred pounds on PCB fabrication and assembly only to find out that the crystals don't work due to the isolated planes and guard rail.

 

But the guidelines recommend this layout, so I am trying to do it correctly especailly if it helps with EMI.

 

Below is an example how I previously designed the board....

 

 

[Mikk Leini]

As always - you know better when you have built it and tested it :)

But before that I would like to point out couple of issues and risks. It appears that you use LQFP64 package. The ground pin you connect to is VSSA (pin 12) like seen on the pinout drawing:

If you look at power supply drawing you see that VSSA is for analog peripherals. Internal oscillators are powered by VDD (and VSS) domain. Unfortunately HSE is not listed and LSE negative terminal is also unknown.

LSE positive supply is VDD/VBAT so very likely ground is VSS and it is also likely that HSE driver uses digital supply like the rest. Nearest VSS to your oscillators is pin 63 which is to other direction from pin 12. Obviously by making ground connection to the wrong ground pin (VSSA) the current loop gets larger than it needs to be and it can make matters even worse. Due to such uncertainty or when chip has many GND pins and it is not known which path of least resistance the current takes, it might be safer to connect your ground island to the MCU ground plane underneath the oscillator traces. Like this:

This gets the edge of my knowledge, but theory states that ground return AC current takes the path underneath forward current path and therefore this way you provide the natural path.

Or you trust the rest of your design to be quiet, and make the "bridge" even larger to also have shortest physical distance to VSS. There's not much else on this side of the MCU so quite unlikely that wide connection is a problem. 

Couple of more things to point out:
1. Your LSE and HSE oscillators share the same ground. They can disturb each other. You should split them up if you want to continue your good practice.

2. Due to manufacturing tolerances and environmental effects I don't trust narrow traces near holes like that single ground connection was. If it is a critical trace I recommend making it wider and/or add teardrops. The single point of ground doesn't need to be super narrow, otherwise it gets to be single point of failure.

3. Proper supply decoupling design is equally important to the stability of the device. All supply pins require close-by decoupling capacitor and current (positive and negative) shall ideally flow underneath the capacitor. Specifically: route +3.3V first to C11 pin 2 and from there take a trace to MCU pin 1. Same story with pins 12/13 and other VDD(A)/VSS(A) pin pairs. See ST AN4488:

4. It appears that you have taken reset signal (which is next to oscillator) upwards, underneath the MCU. Be careful of not splitting up ground planes too much there. Oscillators can be bit further away from MCU so you have room to route out reset signal. Imagine tight BGA packages - they have large fanout designs and work just fine also.

[LCE]

I would only use some GND around the crystals, then make sure that there are no "non-static" signals or power traces routed on the layers below the crystals.

As said above, make sure that no signal at all crosses the GND splits if you use them.

[gbm]

With the boards I designed for L4 few years ago. LSI could not oscillate with a ground plane underneath. The problems disappeared when I removed the ground plane completely - put a "ground-free island" under it.

[Mikk Leini]

Out of curiosity @gbm  - did you remove the ground plane under LSE (right?) from top layer or also from inner layers?

[LCE]

> LSI could not oscillate with a ground plane underneath.

I think most crystal suppliers note that in their datasheets, and that only applies to the outer layer on which the crystal is placed, not to the next inner plane layer. It might add some pF...

But as many of these crystal packages are metallic, I don't put copper underneath them anyway. Never trust the solder mask too much! :D