STM32 MCUs Products

Hi Team, I am designing a custom PCB using STM32H753 and planning to use the QUADSPI peripheral for external memory. My use case is data read/write (indirect mode) — not XIP or memory-mapped execution. While working in STM32CubeMX, I came across some configurations that are confusing, and I’d like to clarify the actual hardware behavior. 1. Dual Bank vs Chip Select behavior In CubeMX, I can configure: QuadSPI Mode: Dual Bank with Quad Lines Chip Select options: Enable Chip Select 1 for both banks Enable Chip Select 2 for both banks Enable Chip Select for each bank My understanding: NCS → Bank1 NCS2 → Bank2 Questions: If I select “Enable Chip Select 1 for both banks”, does this mean: Only one physical flash is used and banks are logical partitions? Or is there any way two physical memories are still utilized? What is the exact meaning of “bank” in this context (hardware vs logical)? 2. BK1_IOx and BK2_IOx pins confusion CubeMX exposes: QUADSPI_BK1_IO0

Hi,I am working with the STM32N6 series MCU on the STM32N6570-DK board and have encountered a pin multiplexing conflict.As per the schematics and datasheet:PA15 (JTDI) and PB4 (JNRST) are multiplexed with LTDC signalsThese pins do not appear to have alternate mappingsMy use case requires:LTDC for driving the displayJTAG for debugging (full JTAG, not just SWD)However, enabling LTDC conflicts with the JTAG interface, specifically JTDI.I have a few questions:Is there any supported way to use both LTDC and full JTAG simultaneously on STM32N6?Are there any alternate pin mappings or remap options available that are not obvious from CubeMX?Is dynamic switching (e.g., using JTAG during debug and reconfiguring pins for LTDC at runtime) a viable or recommended approach?Are there any hardware workarounds or recommended debug strategies for this scenario?I understand that switching to SWD avoids this issue, but I would like to confirm if full JTAG usage is fundamentally incompatible with LTDC on t

Hello ST,What is the maximum current draw into the STM32H563/573's VDDUSB pin, please? Is this the same as IDD(USBBCD), i.e. 300 uA (ds14258 rev.6 Table 120)?

STM32L052TIM21, Channel 1: Output PWMTIM21, Channel 2: Switching between Output PWM and Input CompareSystem Clock: 32 MHzHello,I want to use TIM21 of STM32L052 for PWM output on channel 1 and input capture on channel 2 simultaneously. uint16_t TIM_CCMR1_backup; uint16_t TIM_CCER_backup; // PWM on channel 1 and channel 2 void PWM_init(void) { RCC->APB2ENR |= RCC_APB2ENR_TIM21EN; TIM21->CR1 &= ~TIM_CR1_CEN; TIM21->ARR = 0xFFF; TIM21->CR1 = TIM_CR1_ARPE; // TIM21, channel 1 TIM21->CCMR1 |= (0b111 << TIM_CCMR1_OC1M_Pos); // PWM mode 2 TIM21->CCMR1 |= TIM_CCMR1_OC1PE; // output compare preload enable TIM21->CCR1 = 0; // reset output compare register TIM21->CCER |= TIM_CCER_CC1E; // enable output // TIM21, channel 2 TIM21->CCMR1 |= (0b111 << TIM_CCMR1_OC2M_Pos); // PWM mode 2 TIM21->CCMR1 |= TIM_CCMR1_OC2PE; // output compare preload enable TIM21->CCR2 = 0; // reset output compare register TIM21->CCER |= TIM_CC

The development board I am using is stm32h723. Assuming I only configured region 0 and wrote a blacklist, all regions (both privileged and non-privileged) are inaccessible. The remaining 15 regions were not configured. However, in the MPU Control Mode, I configured "Background Region Privileged access only + MPU Disable during hard fault, NMI and FAULTMASK handlers". This means that for unconfigured regions, only the privileged can access them, and the MPU is disabled during hard faults, NMI, and FAULTMASK handlers. What would happen after this configuration? The CPU is in bare-metal mode without an operating system, and it is in privileged mode. Who should it listen to?

①Fault Phenomenon: The fourth physical output core acquisition pin is faulty. Without any external connections, the voltage at the CPU pin measures around 4.3V, whereas it should normally be 0V. This also causes the operational amplifier chips connected to it to experience overvoltage. After removing the external connected components and chips, the CPU pin still has floating voltage, and the physical output core reads floating values. Replacing the external operational amplifier chips does not resolve the fault. After replacing the CPU chip, the fault is eliminated.②Fault Location: The U8 pin (pin on page 3) is damaged, causing overvoltage to the external op-amps (IC16, IC15) and itself exhibiting floating voltage, which leads to incorrect data acquisition in the physical output core. Meanwhile, the other four physical output core acquisition functions remain normal; only the PA3 channel is damaged.

Could you please tell me how many CAN interfaces are there in STM32H723? I asked the AI, and the AI said there are 2. But when I configured it using Cubemx, I found there are 3. Help me, please!

I'm trying to use the internal CRC calculation unit in the STM32H7 FLASH controller via the HAL_FLASHEx_ComputeCRC() api. I've finally started getting crc32 values returned but can't match them against any common algorithms ... reviewing AN5507 implies it is using poly 0x4c11db7 and maybe initial value 0 ?I had thought it would match the CRC peripheral defaults but this is not the case.Part of my issue may be address bounds, it seems to be inclusive of the start/end addresses so end address is 1 less (though RM indicates bottom 2 bits can't be set so -1,-2,-3 gives the same results). Finally got consistent return values with different burst lengths but still can't matching other algorithms such as those generated by srec_cat with the -STM32 filter.I've seen some comments indicating this may not work at all but the latest errata has nothing about it (STM32H725)It feels like CRC checking of FLASH memory is exactly what this was supposed to be used for but I'm surprised it isn't better do

Currently I am working on STM32H7S78-DK board, In that I am trying to save some data in External flash which will be read over every boot up but while trying to write in specific memory location it will hit to hard fault. I would like to seek clarification regarding write and erase operations on external NOR flash while operating in XIP (memory-mapped) mode on the STM32H7S78-DK.Current Setup:The application is executed directly from external NOR flash (mapped at 0x70000000 via XSPI).Memory-mapped (XIP) mode is enabled for instruction execution.Read operations from external flash are working as expected.Observed Issue:During erase/write operations, the system encounters hangs and eventually enters a Hard Fault condition.Understanding of the Issue:Erase/program operations require switching the XSPI interface from memory-mapped mode to indirect/command mode.During this transition:External flash is not available for instruction fetch.The CPU continues attempting to execute code from the sa

I am working on a custom board with STM32F103CBT6TR. Initially, flashing the code resulted in a Hard Fault error, but now it consistently enters a SIGTRAP even after removing all breakpoints. Additionally, the GPIO pins are not toggling as expected. The code is attached as notepad file for reference. Can someone give a solution to this, thank you. 

I've got some trouble with the CRC unit in an STM32L475.At first, I got wrong CRC results, but then it dawned on me that the compiled code didn't force only 8 bits at a time into CRC->DR. So I added what I've used elsewhere, to force the compiler to store only 8 bits in a 32-bit register.*(__IO uint8_t *)(CRC->DR) = Temp;Temp is a uint8_t variable. Below, it certainly looks like a single byte is transferred to CRC-DR (strb instruction). *(__IO uint8_t *)(CRC->DR) = Temp; 80013ea: 683b ldr r3, [r7, #0] 80013ec: 7018 strb r0, [r3, #0]However, after I modified my code that way, it would seem that nothing is calculated at all. No matter how many (non-zero) bytes I throw into CRC->DR, the output just stays at 0.If I revert back toCRC->DR = Temp;at least I get something, albeit an incorrect value as soon as I enter more than one byte.I initialise the CRC unit like this: CRC->POL = 0x04C11DB7; CRC->INIT = 0; CRC->CR = CRC_CR_RESET;Is there something blatantly obv

I’m choosing a microcontroller for a new STM32 design and I’d appreciate some recommendations.I don’t have particular requirements for compute performance, memory size, or ultra‑low power — just solid peripheral support and a Nucleo board available for development. Required peripherals: 1 × FDCAN (CAN FD) 3 × SPI (in practice only 1 SPI with multiple CS likely) 3 × I2C  Constraints: Prefer MCU in LQFP / QFN (no BGA) Compact (48 pins)  Development on a Nucleo board  I’ve looked at parts like STM32C552VET6 and STM32L552CCT6 as potential targets, but I can’t find a dedicated Nucleo board for them.   Any suggestion? thank you,   best regards,   Gianluca

Split from How to make the FDCAN with DMA - which is solved.TL;DR: STM32s don't support DMA for CAN or FDCAN.Hi, thanks for the clarity.But, the doubt I'm having was, then how to handle that much data rate like eg.5mbps in FDCAN without any help of DMA?In my case, the CPU will be busy with doing other high priority works, so how can I handle the CAN data without the intervention of CPU.Kindly, suggest a way to resolve this. Thanks

I have been using a STM32F469i Disco board to interface with a 800x800 LCD in MIPI DSI video burst mode. In order for this to work from the DISCO board, I have an adapter PCB to connect from the DISCO board to the LCD.It took a while to get going, but the setup with the custom LCD and DISCO board is working fine.I have recently moved to a custom board; I have intentionally made the video dependent aspects of this board the same as the disco board so that I can run my software on either the disco or the custom board without making any changes.The custom board sometimes exhibits odd behaviour when rendering from the SDRAM via the LTDC.Enabling the test colour bars from the DSI always display ok without any problem.From SDRAM/LTDC, the horizontal start point shifts from the left side of the display to some arbitrary location across the width of the display. This occurs randomly, it can be running for hours and remain stable, other times it may shift once, then be stable for a time and may

Hello. Have some issues with MCU ADC configuration and data.Hardware:                                                                                                                                                                                                                                           - MCU: STM32G473MET3                         &

Hello, I have come across an issue with the RTC in my project. In my project I am using the following:- MCU:- STM32H743IIT6 IDE version:- 1.19.0 SDK version:- 1.12.1 I will discuss the issue here, I wrote a program that uses the RTC and print the current time and I tested it straight for 72 hours, what I noticed since the second day that there was a constant drift in time, which kept on changing, and on the last day I observed that there was a total drift of 13 seconds since I started the test. This drift is really concerning for the product that we have made, and that product is already out for field operations. This issue was earlier reported and a ticket was created on ST's online support forum the ticket id is 00255958. They replied to the issue that was reported and asked us to perform the test that I described above, and report this issue over here at ST Community. Please do reply to this message if anyone has any solution for this issue. It is a matter of urgency I a

Hi,I am currently developing a small application with a STM32U5 where I write a few bytes into flash using HAL_FLASH_Program(). All seems to work fine. Except I can only read the data back after I do a reset. I suspect that DCACHE is playing a trick on me? But I am not sure how to invalidate the DCache (preferably only for a small section)SCB_InvalidateDCache();Seems to have some problems on the STM32U5? At least, I was unable to include the prober h-file w/o getting tons of errors. What is the new strategy for cache invalidation? Thanks,Juergen 

Good day folks,I have the DCMI camera interface on a STM32N6 streaming to the SDCard, and I am noticing that there are cases that the DCMI reports an Overrun when a SD access occurs at the same time that the Hsync interrupt was meant to occur.Digging into it I believe its due to congestion on the underlying AXI bus, and the IDMA of the SDMMC taking priority over the DCMI DMA. I have set the DCMI and its DMA to the highest possible priority as below. HAL_NVIC_SetPriority(GPDMA1_Channel12_IRQn, 0, 0); HAL_NVIC_EnableIRQ(GPDMA1_Channel12_IRQn); HAL_NVIC_SetPriority(DCMI_PSSI_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DCMI_PSSI_IRQn); HAL_NVIC_SetPriority(SDMMC1_IRQn, 5, 5); HAL_NVIC_EnableIRQ(SDMMC1_IRQn); gpdma_dcmi.Instance = GPDMA1_Channel12; gpdma_dcmi.Init.Request = GPDMA1_REQUEST_DCMI_PSSI; gpdma_dcmi.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST; gpdma_dcmi.Init.Direction = DMA_PERIPH_TO_MEMORY; gpdma_dcmi.Init.SrcInc = DMA_SINC_FIXED; gpdma_dcmi.Init.DestInc = DMA_DINC_INCREMENTED;

Hello,In my project, I want to hold boot params in BKPSRAM so "Application project" can also write and read this section easily. If boot is needed, "Application project" will set boot params as required and after that it will use "NVIC_System_Reset".Therefore, I tried to write and read some parameters in this area. I can see the datas is written successfully in "BKPSRAM_BASE_S" section while debugging but when I restart the debug session, BKPSRAM section is all fill with zeros. I know that I am missing something but did not find it. - STM32N655 custom board. #define BKP_SRAM_START_ADDRESS ((uint32_t)BKPSRAM_BASE_S) #define BOOT_PARAMS_PTR ((BootParameters_t*)BKP_SRAM_START_ADDRESS) /* USER CODE BEGIN Init */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_RAMCFG_CLK_ENABLE(); __HAL_RCC_BKPSRAM_MEM_CLK_ENABLE(); HAL_PWR_EnableBkUpAccess(); HAL_PWREx_EnableBkupRAMRetention(); /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); /* Configure the per

HI,I am working on a board using STM32H573V and have a working solution with UCPD detecting an inserted memory stick and running the MSC class. In an other part of the software I am using PC9 as an GPIO push-pull, low speed output and as soon as I set it to high, the voltage at PB14 (UCPD CC2) drops from 3.3V to 1.5V and my UCPD handler signals a device attached and turns VBUS on even though nothing is attached. There is no other electrical connection between PC9 and PB14 on the board. I am using a TCPP03-M20 for VBUS switching. The board is acting as VBUS source.

Hello all,I've designed a board around a STM32H743 (LQFP-100) and am running into the following issue.On 2 boards out of 10, the HSE seems not to start properly. The HSE_RDY flag is never set after enabling HSE. I have checked it's not in bypass mode. On the other boards, it works perfectly.The crystal is a ABM3B-8.000MHZ-10-1-U-T and the load caps are 10 pF. We checked possible soldering issues, tested different load cap values just to see, and even replaced the crystal on the failing boards - to no avail.Looking at the OSC_IN/OSC_OUT signals (PH0/PH1) on a scope does not show a significant difference between the working and non-working boards. Maybe just a very slight difference in p-p amplitude.I have looked at the AN2867 app note, and the gain margin seems sufficient according to the formulas given there. I have heard that this crystal may have a bit too high ESR (200 ohm) for the STM32H7 HSE, but again, the gain margin seems alright.Any idea? I have tested with a minimal

Should each vdd pin of the stm32f407zgt6 read continuity like the blue pill on multimeter, are they internally connected within the chip or separated? Similary for all the vss pins are they also all connected vss inside stm32f407zgt6 Thanks

Hello everyone, I am Li Weiwei (李炜炜) from  a company based in Shenzhen, China, specializing in integrated circuit testing equipment and related R&D. We are currently working on a small-scale R&D / prototyping project that requires the STM32F103TBU6 (VFQFPN36 package) in bare die or wafer form (Known Good Die / KGD preferred), rather than packaged chips. Has anyone here successfully sourced STM32F103 series (or similar STM32F1xx) as bare die / wafer through ST directly, authorized distributors (e.g., Avnet, WT Microelectronics, WPG Holdings, Excelpoint, etc.), or other specialized bare die suppliers? Key details I'm looking for: Is the bare die / wafer option officially available for STM32F103TBU6? (I couldn't find it listed on the ST eStore, public datasheets, or standard channels.) Typical MOQ (minimum order quantity) — e.g., full wafer, partial wafer, or small engineering samples (our target: equivalent to 1–5 wafers or a small number of dies for initial prototyping)? R

I tried doing an OBD2 request via Car's OBD2 port.I am able to see the CAN BUS traffic using an oscilloscope , just my request frames are rejected by car. I am using STM32h735G-DK development board to send OBD2 requests. It consists of an inbuilt FDCAN transceiver. Settings are fine (removed termination resistor as car already has two), baudrate is 500kbps  with 87.5% sample point. I am using the following code to send OBD2 request frames:I am able to receive CAN frames and able to log CAN frame frames it is just that frames sent are rejected. What am i doing wrong here?FDCAN Code excerpt: /* ============ 500 kbit/s Bit Timing Derivation ============ * * Step 1: FDCAN Kernel Clock * fCAN = 80 MHz (from Clock Configuration) * * Step 2: Prescaler * Prescaler = 10 * * Step 3: Time Quantum (tq) * tq = Prescaler / fCAN * tq = 10 / 80,000,000 Hz = 0.125 µs = 125 ns * * Step 4: Bit Segments (in TQ) * Sync Segment = 1 TQ (fixed, always 1) * Time Segment 1 = 12 TQ (Prop_

There is something strange happening with STM32N657x0HxQ MCU when HAL tick timer is not using SysTick, but a timer like TIM6, and TIMPRE is changed to 4 or 8 while timer is active. Observed it on DK and custom board.I created isolated test code with CubeMX v6.17.0 for STM32N6570-DK and STM32CubeIDE v2.1.0 to reproduce the issue. IOC file and code in attachment. Test code is in FSBL and it just blinks LED1 with 1 second period. When TIMPRE is 1 or 2, it blinks correctly. To reproduce: Change TIMPRE to 4 or 8 in clock tree and generate + build the code:Power up the board in development mode (BOOT1 = 1). On real application it only happens on cold boot. With this test code it seems to appears all the time.Launch the FSBL with debugger. Debugger should break at HAL_Init(). Press Run. Nothing happens. LED does not blink. Pause debugger and watch uwTick value:CPU is busy in TIM6_IRQHandler and with few seconds, the count has reached 489211. CPU is busy serving only the timer interrupt reques