STM32H753 QUADSPI – Clarification on Dual Bank, IO Lines, and Multi-Flash Possibilities
Hi Team,
I am designing a custom PCB using STM32H753 and planning to use the QUADSPI peripheral for external memory. My use case is data read/write (indirect mode) — not XIP or memory-mapped execution.
While working in STM32CubeMX, I came across some configurations that are confusing, and I’d like to clarify the actual hardware behavior.
1. Dual Bank vs Chip Select behavior
In CubeMX, I can configure:
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QuadSPI Mode: Dual Bank with Quad Lines
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Chip Select options:
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Enable Chip Select 1 for both banks
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Enable Chip Select 2 for both banks
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Enable Chip Select for each bank
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My understanding:
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NCS → Bank1
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NCS2 → Bank2
Questions:
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If I select “Enable Chip Select 1 for both banks”, does this mean:
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Only one physical flash is used and banks are logical partitions?
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Or is there any way two physical memories are still utilized?
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What is the exact meaning of “bank” in this context (hardware vs logical)?
2. BK1_IOx and BK2_IOx pins confusion
CubeMX exposes:
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QUADSPI_BK1_IO0–IO3
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QUADSPI_BK2_IO0–IO3
This gives the impression of 8 data lines (4 per bank).
Questions:
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Are BK1_IOx and BK2_IOx:
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Independent data buses for each bank?
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Or alternate pin mappings of the same internal IO signals?
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If both sets are enabled simultaneously (as CubeMX allows), are these pins internally shorted?
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What is the correct way to route these signals on PCB when using:
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Single flash
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Dual flash (2-chip setup)
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3. Multi-flash usage beyond 2 chips
Given the hardware has:
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1 shared IO bus
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2 chip select lines (NCS, NCS2)
Questions:
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Is it possible in any supported way to interface 4 QSPI flash chips
4. Manual Chip Select using GPIO
Questions:
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Can we use GPIO-controlled chip select instead of the hardware NCS/NCS2 pins in QUADSPI?
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Or is hardware-controlled CS mandatory for correct operation?
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If GPIO CS is used:
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Will timing or protocol issues occur?
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Is it reliable for read/write (non-memory-mapped mode)?
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5. Dual Bank + 1 CS behavior
Questions:
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In dual bank with single CS configuration, is it possible to:
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Read/write data to two different physical chips?
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Or does it always operate on only one physical chip?
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If it is only one chip, is this configuration purely a logical memory split?
6 Extending dual-bank concept
Questions:
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If dual bank works with 2 CS lines (2 chips), is there any way to extend this concept to:
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4 chips (e.g., 2 banks × 2 chips each)?
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Can STM32 QUADSPI handle such a setup in any supported or semi-supported way?
7. Summary of my understanding (please correct if wrong)
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QUADSPI has only one internal 4-bit data bus
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BK1_IOx and BK2_IOx are not independent buses
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True multi-chip support is limited to 2 devices via NCS/NCS2
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“Dual bank with single CS” is logical partitioning, not physical dual memory
I would really appreciate clarification from someone who has worked with this peripheral at hardware level or designed boards using it.
Thanks in advance!
JYOTHISH B CHANDRAN
