32-bit vs 16-bit SDRAM performance for 1024x768 resolution display with STM32H750XBH6

[Geethat]

Split from this thread.

Thank you for your previous responses and guidance.

1. We are now planning to move to the STM32H750XBH6 (BGA package) with a 32-bit SDRAM (IS42S32400J-6TLSDRAM ) interface in our custom board design.
2. Our project uses a 12.1-inch display with a 1024x768 resolution and the RGB to LVDS transmitter ic  which is DS90C385AMTX_NOPB display ic  In our previous design with a 16-bit SDRAM, we observed display rendering and FPS issues, which affected performance. To overcome this, we are considering upgrading to a 32-bit SDRAM for improved rendering speed and smoother graphics performance.
3. Before proceeding further, we would like your confirmation on whether using a 32-bit SDRAM with the STM32H750XBH6 will actually improve the display rendering performance for our 1024x768 resolution.
4. If there is no significant improvement even with 32-bit SDRAM, then moving ahead with this design would not be worthwhile.

Please confirm this so that we can proceed further based on your feedback

[DmitryR]

Good day Geethat,

 

problems of using SDRAM lie often not in the area of bandwidth but in the area of delays. Dynamic memories need refreshing that, if done not properly, may lead to severe delays. If you calculate bandwidth needed for you display you will find out that 16-bit at 100MHz is enough with 50% reserve. FMC may run up to 200MHz so if you experience problems still I do not think that it is bandwidth.

 

And one more advice. Latest STM32H7 chips have LVDS transmitter inside. If you use it you will need to escape about five times less signals for a display from the MCU so that will make PCB routing much more simple.

 

With best regards,

Dmitry

[Geethat]

Thank you very much DmitryR for your reply

As I am not from the firmware side, I didn’t fully understand the detailed points, but I do understand that bandwidth is not the main issue here. However, could you please explain a bit more about the delays related to dynamic memories and how improper refreshing might cause them? A more elaborate explanation would be very helpful for me to understand this better this will help me to analyze our hardware design and overall data flow better.

With best regards,
Geetha

[mƎALLEm]

Hello, 

 

[mƎALLEm]

Hello @Geethat 

This is a new question, you need to ask that in a separate thread.

Thank you for your understanding.