STM32 MCUs Products

Good Morning,   I'm struggling with FDCAN Bus Recovery. The system we have to use consists of an STM32H753-based board and a 3rd party ECU, which is internally terminated via software. Our custom board is also terminated, resulting in the correct 60 Ohm between CAN Hi & CAN Lo. In the event I add an additional termination resistor to the Bus, the power-up sequence doesn't matter, however the bus is the over-terminated, which is obviously not correct. I can, however, see the custom board initially blurting out a CAN frame as fast as it can before the other ECU has finished powering up, and then normal CAN comms is seen on PCAN (the PCAN has been configured to not send any Acks). However, if I leave the bus as it is, it looks like the bus from the perspective of the custom board just turns off. I can see the 3rd party ECU splurging out one of its' messages as fast as it can, however our board should be seeing this message and transmitting Ac

Hello, i am using a stm32f103 mcu to provide rtc functionality. I am using a external crystal  of 32768 hz for the rtc block.The crystal is rated at 6pf load. +/- 20ppm  PN:   QT1C-32.768KDZB-T Apart from this i have also implemented a external gps module   to provide a  "reference time" via uart.Upon power on, the mcu configure the rtc counter with values for  hours,minutes,seconds  taken from the  the gps,   then i just display them on a lcd.My problem is the time drift  on the rtc when comparing the time from the gpsFor example, after 10 hours of functionality,  my  rtc clock drifts with 7-8 seconds when compared with the gps time. I have tried to measure the rtc clock on the tamper pin, and here things start to show upThe measured frequency on the tamper pin ( PC13)    is 512.295hz.

Hi everyone,I am currently trying to measure the CPU temperature using the internal temperature sensor of an STM32F733.I am testing the device inside a climate chamber (oven) to verify the readings. I am fully aware that the datasheet states the sensor is more suitable for detecting temperature variations rather than absolute measurements. However, the values I am getting seem to have a significantly larger offset/gain error than expected.The Setup:MCU: STM32F733Method: To rule out self-heating of the die, the device is kept powered OFF inside the oven until the target ambient temperature is reached and stabilized. I then power it on and immediately take the ADC measurement.Vref+: Connected to external reference voltage (2.048V).The Observations:Oven at

Hello,I dug deeper into PSSI behavior, and and I observed unwanted behavior. From my point of view it is a bug.PSSI is configured as:OUTEN = 1 (transmit mode)CKPOL = 0 (outputs driven on rising edge, inputs sampled on falling edge)RDYPOL = 0 (0 at input indicates that the receiver is ready to receive)DEPOL = 0 (0 at output indicates that data is valid)DERDYCFG = 0b11 (Both PSSI_RDY and PSSI_DE alternate functions enabled)EDM = 0b00 (Interface captures 8-bit data on every parallel data clock)Chip STM32H7R3Z8T6, clocked at 600MHz from HSI, placed at PCB, powered by 3.3VPSSI kernel clocked by 150MHz and 300MHz (PLL from HSI)Transmitted data is rising numbers from 0 to 15, stored in array in AHBSRAM1, manualy written by core to PSSI->DR as 32bit values (four data bytes at one write). See source code:

Hi,We have STM32N6570-DK and are testing camera input, video encode and write to SD cardWe have not been able to make the "VENC_SDCard_Appli" example work, the SD card just contains zeros.The "VENC_SDCard_ThreadX" example does work however, resulting in an 800x480 video.Are there any examples on encoding at 1080p resolution? Changing the encoder parameters and level results in memory allocation failures in EncAsicMemAlloc_V2.Many thanks 

I have a new board design that interfaces an STM32L4A6 with a uSD card using 1.8V I/O. The SD Card is powered by 3.3V and supports the LVS mode of SD. The STM32L4 does not seem take account the SD specification 6.0. There is no auto detection mecanism of the signalling voltage level in this MCU. This MCU can not start in UHS-I 1.8V mode.Do you know a MCU which can start the LVS identification sequence ?

I have updated the STM32L4 HAL drivers to V1.13.6 / 14-November-2025 (1.18.2), which has broken my implementation of HAL_UARTEx_ReceiveToIdle_DMA.Is this a fault in the new HAL drivers or does user code need to be updated inside the HAL_UARTEx_RxEventCallback?

I have an STM32L011F4P6 with an RTC.  It is running at 3.3V and 16 MHz off the internal HSI RC clock.  The RTC is driven by a +/-20ppm 32.768 KHz crystal.  It is running at room temperature (23-25C).  After calibration, I am losing several seconds per day!  What's wrong?Here's more information:I have a auto-calibration routine where it will output a 1Hz signal on PA2 and capture the rising edges using TIM2 channel 3, running at 16 MHz.  I capture the start time (1st edge), I interrupt on overflow and add 65536 to a 32bit variable, and I capture the final (33rd) edge to get the total number of 16MHz clocks in 32 seconds according to the RTC.  At the same time, I have a GPS module with a 1Hz output fed into PA10.  I set up TIM21 channel 1 identically to the TIM2 setup, to capture the total number of 16MHz clocks in 32 seconds according to the GPS.I take the two numbers and find the difference, not in PPM but in

Is there a comprehensive single documentation source of the Flash layout for say, an STM32H563?The documentation I find is very opaque.  Questions I have at present (From a non secure perspective):1. Where is OBK located? (0x0BF0000 to 0x0BF9FFFF ???)2. Where is system located?3. Is RSSLIB actually using OBK memory? Or is this located somewhere else?4. Is there a way to self program the debug password for PRODUCT_STATE > OPEN?5. If #5 true, are there some real docs on this?  All I find so far is tutorials and code for the 573 in a secure perspective. 

Hello,I want to add a software update feature to my device, but I am unsure about the correct way to verify a newly installed firmware image. My goal is to make sure that the entire firmware has been written correctly and is not corrupted before the bootloader starts using it.One idea I have is to calculate a CRC of the whole application at build time and store this CRC at the end of the application image in flash. Then, during boot, the bootloader would calculate the CRC of the application in flash and compare it with the stored value to decide whether the firmware is valid. However, I am not sure if modifying or reserving a part of the application flash for this purpose is a good or recommended approach.Are there more common or reliable methods to verify a newly installed firmware before activating it? How is this typically handled in bootloader-based firmware update systems?

Hi,I am getting a warning "The core is locked up" and a few more (please refer to the attached image).I have also tried flashing with the hex file, but some flashing issue is observed.

Hello!I am interfacing an ADS131M02 ADC to the STM32C0116-DK board using SPI for a project I am developing on live streamings. I am able to read SPI Data using the HAL polling functions (HAL_SPI_TransmitReceive), however that created unwanted delay between bytes and I tried swithing to DMA to improve performance. Configuration:All clock to max (48MHz)SPI: Full-Duplex Master, 8bits, Mode 01, DMA Tx + DMA RxPrescaler 2: BaudRate 24 MBits/s -> FAILPrescaler 4-Max: SUCCESSThis is the result with prescaler set to 4 (12 Mbits/s). (Pink: MISO, Blue: SCK), the data is correct.

I am working on the NUCLEO-H755ZI-Q, which contains a dual-core STM32H755 (Cortex-M7 + Cortex-M4). I configure the system clocks in CubeMX as follows: SPI1/2/3 Clock MUX: 400 MHz System Clock: Configured for high-speed operation CM7 core frequency: Correctly matches the configured value (e.g., 200 MHz / 400 MHz depending on settings) However, when I debug or read the CM4 core clock, I always see: CM4 clock = 64 MHz It does NOT increase even when I configure higher values in CubeMX.  Regards, Prathiksha

Hy,we are about to create a Proof-of-concept system for a camera application. We want to use STM32N6 Nucleo-144 board (MB1940) Board and add a extension board to CN2, CN3, CN15 and CN16. The project needs Ethernet (which we want to use from Nucleo Board) and PSSI16 Bit (which we want to realize on the extension board).I create a CubeMX project from scratch and select Nucleo Board as starting point.I am not able to configure both, Ethernet and 16 bit PSSI. When I start from the controller itself (no Nucleo) it seems to workWhat do I miss?Best regardsHarald 

Sequent Microsystems designs and sells Automation Systems using Raspberry Pi. All our products use STM processors. We use about 10,000 processors per year in different configurations. Generally we do not have any quality problems, but occasionally we run into a defective lot. On a recent run of 30 prototypes using STM32G431CBT6, 50% were defective. We replaced the processors and all boards worked as expected. We buy all out processors from a Chinese distributor.We saved the defective processors and I would like to know if you would have any interest in inspecting them to find out why they entered the distribution chain, and to advise us how to avoid this problem in the future. Mihai BeffaCEOSequent Microsystems

Bit-banding Alternatives for Modern ARM Cores Background Information: The bit-banding feature available in ARM Cortex-M cores (ARMv7-M architecture including Cortex-M3 and Cortex-M4) provides hardware-level mapping of individual bits within a 1 MB memory region to words in a 32 MB alias region. This mechanism enables atomic bit manipulation without requiring read-modify-write operations.   Specific Query: For ARM Cortex cores beyond M7 architecture that do not support the bit-banding feature, could you please provide detailed information regarding:   Available alternative methods for atomic bit manipulation Performance implications of these alternatives Recommended implementation strategies for maintaining atomic operations Code examples demonstrating these alternative approaches Request for Documentation

Hello, I wanna use the development board STM32N6570-DK for taking a picture with MB1854B. i am quite new for DCMI and DCMIPP. i just want to read the image through the pipe1 of dcmipp but i dont know how to config the MCU in .ioc file. Can anyone explain or give me an example for that? 

I am using a Nucleo-N657X0-Q board to prototype a data collection system that collects samples from an ADC connected to the SAI peripheral and places the results in RAM. If I use CPU AXI RAM0 as the destination this works correctly, but if I change the destination to DTCM all I get is a buffer full of zeroes.According to chapter-17 of the ref manual, HPDMA1 AXI port has access to the DTCM and I am setting the DAP field of HPDMA-CH0 TR1 register to Port-0 as required (setting it wrong results in a DTEF interrupt).I have RISAF 1 and RISAF 2 set as follows: RISAF1->REG[0].CFGR = 0x00000000; RISAF1->REG[0].CIDCFGR = 0x00FF00FF; /* RW for everyone */ RISAF1->REG[0].STARTR = 0; RISAF1->REG[0].ENDR = 0xFFFFFFFF; /* all-encompassing */ RISAF1->REG[0].CFGR = 0x00000101; /* enabled, secure, unprivileged for everyone */ RISAF2->REG[0].CFGR = 0x00000000; RISAF2->REG[0].CIDCFGR = 0x00FF00FF; /* RW for eve

Hi,I am currently working on the firmware of a PCB with an STM32G031K8T6 as the MCU, supplied by a 1.8V voltage.When I enter Stop 1 mode, the consumption of the MCU drops to 100uA, instead of the 7uA stated in the datasheet.The app_stop function is as follows :void app_stop(void) { timer_uninit(); i2c_slave_uninit(); i2c_master_uninit(); gpio_stop_mode(); HAL_SuspendTick(); SystemClock_Config_StopMode(); HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); } void gpio_stop_mode(void) { GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = GPIO_PIN_All; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); GPIO_InitStruct.Pin = GPIO_PIN_All; GPIO_InitStruct.Pin &= ~(GPIO_WAKEUP_PIN); GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL

Hello everyone,We are experiencing an issue with a product that integrates an STM32H562ZG microcontroller.Our development environment consists of IAR Embedded Workbench 9.70.1, with the project configured using CMake.Currently, we are observing unexpected behavior during debugging. Specifically, after downloading the firmware using IAR and ST-Link V2 and starting the debug session, the application immediately jumps to NMI_Handler().Unfortunately, even after modifying the code, reflashing the microcontroller, and restarting the debug session, the firmware still ends up in NMI_Handler().Performing a full chip erase and reprogramming with IAR resolves the issue,  it becomes inefficient and problematic for debugging because any time the code is modified a full chip erase is needed to make all work.We have seen something related to ECC flash check but we don't know if c

I’m working on an STM32H7R7 project using SDMMC1 + FreeRTOS (CMSIS-RTOS v2) + FatFs, all generated with STM32CubeMX.I’m facing an issue where f_mount(opt=0) works, but the system blocks inside f_open() and never returns, so the return value cannot be checked.A key aspect of the problem is that the behavior depends on how the device is started:After flashing the firmware with a debugger connected and running immediately, the system behaves differently.After a cold power-up (power removed and re-applied, no debugger connected), the same binary consistently freezes when reaching f_open().In both cases:The code is identicalThe clock configuration and FreeRTOS setup are unchangedNo additional initialization is performed when the debugger is attach

 I am working with an STM32F0 device and I want to implement a firmware update mechanism.My current plan is to split the internal flash into three regions:Bootloader: 0x08000000Application Slot 1 (App1): 0x08004000Application Slot 2 (App2): 0x08008000The bootloader always runs first.Only one application slot is active at a time.The update flow is planned as follows:If App1 is currently running and a new firmware update arrives, the new firmware is written to App2.If App2 is running, the new firmware is written to App1.After the update, the bootloader selects which slot to boot.My concern is about the linker script (.ld) configuration:When I build a new application firmware, I set the flash origin address in the linker script to:  

I am working on an STM32N6 hardware design, and have reviewed both development kit reference designs (MB1939/MB1940). Both designs use the same power supply scheme, when using internal SMPS it has 2x 3V3 regulators and 3x 1V8 regulators.I am interested in combining several power supplies if possible, notably:1. Is it possible to tie all 3V3 together?While AN5967 suggests to apply VDD33USB in the last step of power sequencing, the VDD33USB supply is noted to be independent of the other supplies within the N6, just like the VDDIOx supplies. The reference designs have tied VDDIO4 to VDD at 3.3V, which makes me believe I could also combine VDD33USB and VDD.Aside from just VDD33USB and VDD, all the 3.3V peripherals on the dev kits come from the second 3V3 supply, can I tie all peripheral 3V3 to VDD33USB and VDD, so I have a single 3V3 rail on the PCB?If not what about the STM32N6 disallows this?2. Can I combine 1V8 for p

Experimenting with STM32F427 and STM32F446 I found out, that the RCC_CR.HSEBYP bit is *not* reset by Software reset. It is reset only by NRST and Power-On reset.While applications where this could lead to problems (i.e. where HSE clock source is changed on-the-fly and software after performing Software reset relies on reset state of this bit) are probably very rare, it may result in an "interesting" surprise if one stumbles upon it, and deserves to be documented.Can ST please confirm/explain and document?Thanks,JW

Hello sir/miss , According to the STM32H7 datasheet, the range of the HSE external crystal oscillator is 4M - 48MHz. However, when we used the STM32H7IIT6-EVAL evaluation board and replaced the original 25MHz surface mount passive crystal oscillator with a 48MHz passive crystal oscillator, we were unable to obtain the corresponding 48MHz frequency from the MCO-PA8 pin. Summary: All conventional passive crystals from 4M to 40MHz were tried and worked fine. However, for external passive crystals above 40MHz , just like 48MHz, the MCO output waveform frequency was 16MHz, which is 1/3 of the HSE frequency, and it was unable to output 48MHz. Please provide a solution or suggest areas where we can improve the test. Thank you very much!