RTC frequency not accurate on STM32F103C8 - high ppm value on tamper pin

[Bogdan]

Hello,

 

i am using a stm32f103 mcu to provide rtc functionality.

 

I am using a external crystal  of 32768 hz for the rtc block.

The crystal is rated at 6pf load. +/- 20ppm  PN:   QT1C-32.768KDZB-T

 

Apart from this i have also implemented a external gps module   to provide a  "reference time" via uart.

Upon power on, the mcu configure the rtc counter with values for  hours,minutes,seconds  taken from the  the gps,   then i just display them on a lcd.

My problem is the time drift  on the rtc when comparing the time from the gps

For example, after 10 hours of functionality,  my  rtc clock drifts with 7-8 seconds when compared with the gps time.

 

I have tried to measure the rtc clock on the tamper pin, and here things start to show up

The measured frequency on the tamper pin ( PC13)    is 512.295hz.

this is giving a huge ppm diference   of about 576 ppm.

 

I have tried with several instruments to measure the tamper frequency,  but all are measuring mostly the same deviation of  .295 hz

 

I have also tried a workarround to disable all the remaining preripherals, leaving only the rtc functionality,  the same tamper freq deviation is measured.

I have also tried to create a simple CubeMX project only with the rtc tamper functionality, and the same deviation is measured

 

To be honest i am starting to run out of ideas, any sugestions could help.

a insight of the pcb layout for the X1  rtc crystal.

[RobK1]

Where are the load capacitors for the crystal?

[Peter BENSCH]

There are a few uncertainties:

• Are you absolutely sure that this is a genuine device and not one of the many counterfeits produced by Asian manufacturers?
• The measured +576 ppm at PC13 corresponds to a deviation of almost 21 seconds over a 10-hour measurement period, but you observed 7...8 seconds?
• Your layout is only shown for the crystal X1 and does not include the additional layers between X1 and MCU?
• What type of load capacitors are used?

With regard to the layout in particular, please refer to Appnote AN2867, which provides further information. The community also offers several tips on how to lay out the highly sensitive LSE, e.g. in this Knowledge Base article or here.

Regards
/Peter

[Bogdan]

Hello Peter,

the device is genuine. I have a stock of them from a uk distribuitor, bought some years ago.

Concerning the layout,   there are no aditional layers conected to the crystal.   Underneath  the top layer there is only a solid GND layer.

What concerns me is Robk1 remark regarding the external capacitors wich i have not considered in the design, i am not sure if these are mandatory.

I will study the AN2867 document aswell.

I will try to port the SW to another board using the same mcu,  and this one has footprints for the crystal capacitors.

I will come back with details