A Question regarding DMA controller trigger source

[JC1985]

Hi, STM experts, 

This question is regarding STM32L4 series MCU. It is about DMA controller's trigger.

Let's say we have two DMA channel, DMA_A and DMA_B. Is it possible to configure the system so that when DMA_A's task is finished, DMA_A send a trigger to start DMA_B which is programmed with a different task. In the whole process, we expect that there is no CPU involvement.

Thanks!

// JC1985

[Sarra.S]

Hello @JC1985, 

>>to start DMA_B which is programmed with a different task

by different task, you mean different peripheral, different DMA stream? In that case that is not possible;

Only a single channel can be selected for each stream. Of course if you are not transmitting on both ports at the same time, then you can switch back and forth between channels.

According to RM0351: "A same peripheral request can be assigned to two different channels only if the application
ensures that these channels are not requested to be served at the same time. In other
words, if two different channels receive a same asserted peripheral request at the same
time, an unpredictable DMA hardware behavior occurs."

[JC1985]

Hi, Sarra,

Thanks for your answer, maybe I didnot make it clear. Let me re-describe my question using an example.

Let's say we have two DMA channels DMA-A, DMA-B. What we want to achieve is that:

1. DMA-A is configured to move let's say 20 bytes of data from SRAM location A1 to SRAM location A2.

2. DMA-B is configured to move let's say 5 bytes of data from SRAM location B1 to SRAM location B2.

3. We first start DMA-A and we expect that when DMA-A finishes the task in item 1, it generates a trigger event to start DMA-B. And DMA-B will then start to do task as described in item 2. After item 2 task is done by DMA it generates one interrupt to CPU.

Could you please help check if the above requirement can be achieved by ST32L4 MCU?

Thanks!

// JC1985

 

 

 

[waclawek.jan]

> if the above requirement can be achieved by ST32L4 MCU?

No.

DMA channels have no triggers from other DMA channels completion, see DMA request mapping subchapter of DMA chapter in RM0351.

You did not tell us enough of your application (not even the particular STM32 model) to judge, whether it may be able to achieve something similar to what you describe e.g. using cascaded timers.

JW

 

[JC1985]

hi, JW, 

Thanks for your reply. The MCU we are using is STM32L4R9ZIY6 FYI. The actual use senario is as folllows:

We want to implement an low CPU loading error handling mechanisim based on I2C communcation.

We define the data packet of I2C as a fixed-size let's say 33 bytes and the first 32 bytes are payload data and one checksum byte as the 32th byte. The 33rd byte is a dummy byte which is used for collecting a ACK or NACK bit from receiver to show if the entire packet is valid or not.

At the receiver side, two DMA channels, A and B are used. DMA-A is programmed to work with I2C receiver and its task is to receive the first 32 bytes without interfering CPU. Within this period, the I2C controller is configured as auto ACK reply mode. By our design, when DMA-A finish its job, it generates a trigger upon receiving the 32nd byte to start DMA-B which is programed to move the data from SRAM to I2C controller mode register to change the ACK mode from AUTO to CPU mode. Upon the arrival of the 33rd byte, the dummy byte, CPU is interrupted and start to validate the integrity of the first 32 bytes. Based on the validation result, CPU reply the ACK or NACK to inform sender if the packet is ok or need resend.

This is our real and original requirement, any comment or idea to realize it on L4R9?

Thanks!

// JC1985

 

[waclawek.jan]

 @JC1985 ,

In certain way, the 'L4Rx don't belong to 'L4 family; ST calls them 'L4+. One of the major differences is, that instead of the fixed DMA trigger multiplexers built into DMA itself, the  'L4+ have DMAMUX unit which not only represents a matrix to select triggers into DMA channels but also has a relatively complex request generator and synchronization features.So maybe that could be used in some way - read the DMAMUX chapter in RM; I am not familiar with it enough to judge whether that's the way to solve your problem.

If the I2C is slave receiver, you may want to have a look at Slave Byte Control mode subchapter of I2C chapter in RM.

JW