Hello and welcome to the community.
I can give a raw steps:
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Define a shared memory region: Choose a memory region that is accessible by both cores (for example DTCM is not accessible by CM4). You can for example use SRAM3 for this purpose.
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Place your variable in the shared memory: define the variable in a specific section of the memory that is designated for shared access. Ex: SRAM3. This is done using linker script or pragmas depending on your development environment.
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Ensure Cache coherency: Since CM7 core has a cache, it's important to manage cache coherency for the shared memory region. You may need to disable caching or explicitly manage cache operations using the MPU.
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Synchronize access: Use a synchronization mechanism to prevent race conditions. The Hardware Semaphore (HSEM) can be used to ensure that only one core accesses the shared memory at a time.
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Initialize variable in CM7 Core: Write the initial value to the shared variable using the CM7 core.
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Access variable in CM4 Core: After ensuring that the CM7 core has released the semaphore, the CM4 core can read the shared variable.
Here is an example of how you might define and access a shared variable in C code:
// Define the shared variable (place in shared memory section using linker script or pragmas)
volatile int shared_variable __attribute__((section(".shared_memory")));
void M7_Core_Init(void) {
// Initialize the shared variable
shared_variable = 42;
// Ensure the variable is written to shared memory before semaphore release
__DSB();
// Release the semaphore to allow M4 to access the shared variable
HAL_HSEM_Release(Your_HSEM_ID, 0);
}
void M4_Core_Access(void) {
// Take the semaphore to ensure safe access to the shared variable
HAL_HSEM_Take(Your_HSEM_ID, 0);
// Access the shared variable
int value = shared_variable;
// Release the semaphore after accessing the shared variable
HAL_HSEM_Release(Your_HSEM_ID, 0);
}
In the above code, replace Your_HSEM_ID with the actual semaphore ID you are using. Also, ensure that the shared memory section (.shared_memory) is properly defined in your linker script to be in the SRAM3 region.
PS: you can also use OpenAMP for more advanced data sharing between cores. Some examples are available on STM32H7Cube on this link: https://github.com/STMicroelectronics/STM32CubeH7/tree/master/Projects/STM32H747I-EVAL/Applications/OpenAMP
Hope I answered your question.