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Visitor II
July 9, 2024
Question

ADC Conversion Time STM32H563

  • July 9, 2024
  • 13 replies
  • 2860 views

ADC1 clocked @ 65 MHz, pre-scaler of 8, 7 channels active, 640.5 cycles/conversion, 256 oversampling, interrupts, scan mode. The numbers suggest all channels will be converted 1x in (8/65000000) * 640.5 * 7 * 256 = 141 ms. But when I look at uwTick before HAL_ADC_Start_IT() and after 7 conversions complete, I get 37 ms. Why the discrepancy?

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    13 replies

    Graduate II
    July 9, 2024

    I have no idea. But 65*(141/37)=247Mhz =~ 250Mhz, the max Freq for this chip.

    Are you sure the ADC clock is running at 65Mhz and not 250Mhz? If you're using cube, can you share a screenshot of your clock configuration? and ADC peripheral as well.

    Super User
    July 10, 2024

    Why the discrepancy?

    Probably the clock is not what you think it is. Impossible for us to tell here. Math otherwise seems okay, except:

    Note that the 640.5 cycles is only for sampling. There is an additional 12.5 cycles/sample for conversion at 12 bits.

    Graduate II
    July 10, 2024

    That fits. (8/65000000) * (640.5+12.5) * 7* 256 *1000 = 144.02 = 37*4 

    mccabehmAuthor
    Visitor II
    July 10, 2024

    Where is the factor of 4 from? As in 144 ~= 37 * 4

    mccabehm_0-1720616679302.png

     

     

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    mccabehm_4-1720616857794.png

     

    mccabehm_5-1720616903171.png

     

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    Graduate II
    July 10, 2024

    I don't see anything obviously wrong with your configuration. Can you post the entire clock screen?  (PLL sections, HCLK).

    This might happen if you set the HSE crystal frequency to the wrong value (e.g. you tell Cube you're using a 4Mhz  crystal when in fact it is 16Mhz), so the PLL input frequency is actually 4x. 

     

    Also, what happens if you switch to the Synchro clock mode (which uses the the AHB clock)? 

     

    Update: no reason to accept as solution yet. Feel free to unaccept until resolved.

    mccabehmAuthor
    Visitor II
    July 10, 2024

    mccabehm_0-1720626821635.png

     

    mccabehmAuthor
    Visitor II
    July 10, 2024

    Verified HSE is 26 MHz

    Graduate II
    July 10, 2024

    Also, what happens if you switch to the Synchro clock mode (which uses the the AHB clock)? 

    mccabehmAuthor
    Visitor II
    July 11, 2024

    Synchronous clock mode divided by 4 results in 18 ticks (ms) for the same conversions.

    Graduate II
    July 11, 2024

    Which is exactly what you'd expect if HCLK was around 250Mhz, and there's no mystery x4.

    So It still looks like (in async clock mode) the clock going to ADC is not at 65Mhz, but 4 times that.

    Can you paste the contents of the HAL_ADC_MspInit() function (it's in Core/src/xxx_hal_msp.c)? and your .ioc file?

     

    Also, please unaccept the solution - we're not there yet and it's in your interest to have others on the forum look at this, they may recognize the issue immediately.