ADC DC-bias auto-adjusts above 0 volts on F4 and H7, is there any documentation?

[Robmar]

Both F407 and H743 ADC input add DC-bias to AC connected inputs, very handy, but I would like to have the specifications for this feature, perhaps even a circuit diagram explaining how the MCU averages the AC input above ground as needed.

I have read the Intro to ADCs AN4861 and the datasheets but must have overlooked the relevant information.

[TDK]

There's no internal DC bias happening except through the protection diodes, though I wouldn't really call that DC biasing. You need to DC-bias the signal after the AC coupling capacitor with a resistor bridge.

[Robmar]

We have DC bias resistors on the boards but it works perfectly without.

The protection diodes will of course stop currents from negative voltages entering the chip, but how would they raise the pin voltage by in our case, 0.6 volts?

 

[waclawek.jan]

ADC sampling capacitor is during conversion charged to an unspecified potential (maybe VREF+/2, maybe not, I am not an expert), which it then dumps into your decoupling capacitor. Under certain circumstances that might mimic DC bias.

JW

[Robmar]

Sure, but as the topic states, I'm looking for technical facts, not gossip!! haha.  This needs to be detailed, and I can't find any real details on the ADC input circuit.

[Robmar]

Thinking about this, the sampling capacitor is charged by the positive current from our input signal due to diode protection, which is always half the average signal voltage.

That would then automatically bias our AC input signal to just were it's needed regardless of amplitude (up to Vref/2 of course).

In that case, why even bother with bias resistors?

But how can the pin voltage shift positive as it's blocked by the protection diode, no?

[TDK]

The protection diodes won't do that, but a floating input will be influenced by any number of things. You're probably primarily seeing:

• Injected current from sampling switch (see section 4.4 in pdf, especially 4.4.4)

https://www.st.com/resource/en/application_note/an2834-how-to-optimize-the-adc-accuracy-in-the-stm32-mcus-stmicroelectronics.pdf

That, plus the protection diodes, will cause the voltage to drift to somewhere above GND. How much depends on circuit capacitance, sampling time, and other things.

Also note that nothing is truly isolated, so there will exist a path to GND or VCC or some other voltage which will slowly cause the voltage to drift.

[Robmar]

Okay, hard facts, thanks.

So that app note says the ADC input circuit is "not perfect" that the input switch has capacitance on the two transistors, and "Practically the firmware must not program the ADC in continuous mode but only in single mode and must ensure that there will be a time gap between conversions with duration
equal to tC."

So and how can we do that when sampling two signals at 384 KHz?

[TDK]

That wasn't a blanket requirement, but rather a suggestion to solve a specific case. There are other solutions suggested as well.

If you're happy with the quality of the data coming in without DC biasing, and the risks that come with it, you can get away without it. Take care to limit the amount of injected current to datasheet limits. Without DC biasing, you won't know exactly where the input range is and can cause the signal to be outside of the limits. Particularly startup/shutdown or other spikes could cause issues. The protection diodes will only bring it up to around -0.3V (or down to (VDDA + 0.3). Maybe it'll work for a while and fail. Maybe it'll work forever. Up to you if you want to accept that risk.

[Robmar]

I'm seeing the unconnected ADC direct inputs floating at around 0.6 volts actually, double the figure you give, why would that be?
You say there are other solutions available to remove this uncharacterised DC bias, but what other solution could effectively work in our real world application?

[Robmar]

We do of course have to use DMA for the sampling of the two streams because we don't have the option to use the H743 as an ADC, it has to earn it's keep handling many noisy tasks from updating the external LCD via LTDC over 16 lines (RGB565), and run USB coms and audio.

You're going to tell me there is no solution I think.  Still it is very convenient that the voltage "slowly drifts" to the centre of our AC signal voltage, almost by design!

Our DC bias correction code works on each batch of samples, so corrects as it goes, of course if we centre bias the input signal to VDD/2 (1.65v) then the offset will be fixed.

Of course the bias resistors will add noise to the input signals, so what is the down-side of letting it automatically centre the DC offset?

 

[waclawek.jan]

>>  ADC sampling capacitor is during conversion charged to an unspecified potential (maybe VREF+/2, maybe not, I am not an expert), which it then dumps into your decoupling capacitor. Under certain circumstances that might mimic DC bias.

> Sure, but as the topic states, I'm looking for technical facts, not gossip!! haha. This needs to be detailed, and I can't find any real details on the ADC input circuit.

That's not gossip, that's the facts, and that's all of them, repeated through the DS and ANs. The ADC input circuit consists of one single capacitor (you'll find its capacitance in the DS), and a switch, which connects it during sampling period to the input pin.

Sure, there are protection circuits with leakages and other surrounding sources of leakage and crosstalk. Leakages are specified in the DS, too (e.g. +-1uA in case of 'F407, although that's a max. for all sorts of circumstances;  for pin set to Analog it will be significantly less, e.g. 'F303 specifies +-0.2uA, it's not specified separately for 'F407 as it's not intended typically for analog usage, and there are costs associated with this kind of specifications, as the manufacturer has to test them). Note, that it's given as +-, i.e. there's no single specified "source voltages", as this leakage adds up from various sources, and they again vary according to circumstances (e.g. there's a contribution from the neighbouring pin, so the leakage depends on how that pin is set up and used). Btw. you have leakages in your circuitry (decoupling capacitor, PCB itself together with whatever surface impurities present such as soldering residui), too.

So, the DC "bias" you see accidentally adds up from these leakages and the charge dumped from the sampling capacitor during conversions. It depends on the particularities of your application.

Your input circuitry has to be designed so that whatever the actual leakage is, and whatever charge state of sampling capacitor at the beginning of the sampling period is, during the sampling period the input circuit delivers the charge needed to charge/discharge the sampling capacitor to the voltage you want to measure. Again, this is the full information you need.

If this information results in the corollary that the decoupling capacitor alone won't cut it, then that's it. Btw. this information also tells you, what value of bias resistor you need to maintain a chosen DC offset. That resistor together with the decoupling capacitor (and its leakage) of course introduces a LF rolloff; if that won't suit your purpose, again, that's it, and you have to design a different input circuit arrangement.

JW

 

[Robmar]

You wrote "I am not an expert", "I think...", I wrote "I need hard facts", so thanks for your view.

[waclawek.jan]

I took the code from https://community.st.com/t5/stm32-mcus-products/adc-in-stm32f446re/m-p/613434/highlight/true#M228331 and modified it so that it performs conversion infinitely. On a 'F407 Disco, this results on a cca 0.6V on PA1 (which is not connected to any other circuitry on the 'F407 Disco, just the pinheader). It's a "steady" 0.6V, with no visible spikes from sampling, so it could be assumed, that that's the voltage to which the sampling capacitor is charged during conversion, dumped to the parasitics of the pin during the repeated conversion.

Then I modified the code further so that it performs one conversion, waits cca 250us then performs second conversion and then stops. The resulting waveform is here:

The "stable state non-conversion" DC offset is cca 40mV, that's given by the leakages. The charge dumped from the sampling capacitor to the parasitic capacitance (pin and tracks and the probe and scope input) increases its voltage by around 130mV which is around 1/5 of what we assume is on the sampling capacitor at the end of conversion (and we assume it won't leak significantly between end of conversion and start of next conversion's sampling), so if the sampling capacitor is 6pF, the parasitics are around 30pF (the pin's parasitics is given as 5pF, scope's input is spec'd at 18pF probe is 1:10 and its input is spec'd at 14pF, so that's together with some track etc. parasitics is around correct). This discharges to the leakage with tau of cca 200us, so the leakage is cca 6MOhm; but there's 10MOhm of scope+probe, so the pin's true leakage is at around 10MOhm too, or around 0.3uA at 3V, which again sounds about right.

JW

[Robmar]

As I mentioned earlier, 0.6v is what I am also seeing on the F407 disconnected ADC inputs in continuous mode.

The one shot and wait mode is really not helpful in anyway for any application that I can think of, certainly not for fast signal conversions.

I guess there isn't an expert on the ADCs available who can really answer this point, ST often sub-contracts ADC design, USB too, so there are no experts in house.

There probably isn't a good solution, as the application note on ADCs optimisation says, the ADCs are not perfect.

That said if any ST engineers have any hard facts and the ideal solution, please post.

[TDK]

> I'm seeing the unconnected ADC direct inputs floating at around 0.6 volts actually, double the figure you give, why would that be?

I never said it would bring it up to 0.3 V. Perhaps re-read.

> There probably isn't a good solution, as the application note on ADCs optimisation says, the ADCs are not perfect.

You do realize that NO ADCs are perfect, right? I'm not sure why this is such a revelation to you.

[Piranha]

I was wrong in assuming that you are not trying to find an inappropriate magic bullet. ;) Anyway, adding an external capacitor increases the allowed driver impedance at the expense of adding an additional charge time, which, of course, decreases the achievable sample rate. Those are not device limitations, but a generic rules of physics. The only thing specific to STM32 is the ADC input capacitance of 4 pF. Even taking the whole sampling period of 2,6 us and calculating the impedance for 12-bit resolution requires no more than 72 kR impedance. That is a number, which is a hard limit and there is no way around it. And even that impedance is far from the one provided by the leakage currents, but the actual sampling time and required impedance will be even smaller.

On the bright side there are plenty of small, cheap, single supply, low voltage, rail-to-rail op-amps out there.

P.S. I do agree about ST's broken bloatware and general negligence towards the software. Probably I'm the hardest and loudest critic for it. But all of it is just a consequence of the prolonged western leftist socialist politics...

[Robmar]

Putting the personal ego away for a moment, you haven't troubled to read the details of our application.

What capacitance do you suggest we add to maximise the design for dual-ADC channel 384 KHz radio signal sampling on an MCU that is controlling two LCDs, serial communications, USB and FFT signal processing?  I look forward to being impressed by your design acumen!

PS We already have 47pF on the ADC inputs to ground.

[Piranha]

Other peripherals and how you are processing the captured signals are irrelevant for this.

It's you, who "suggested" adding an additional capacitor, not me. Your text about the "time gap" is a quote from AN2834 section 4.4.3 part "Workaround for extra high impedance sources". That section talks about a workaround to increase the impedance requirement by adding an additional large capacitor. That text is about that particular workaround, not ADC in general. The fact that now you are wondering what additional capacitor I am talking about, shows that you haven't actually read or understood that particular section of the AN2834. And then it turns out you already have some capacitor... But we don't know the purpose of it. Is it a part of a low-pass anti-aliasing filter? Is it there to increase the allowable impedance?

[Robmar]

What a pity, and there I was thinking you'd surprise me with an enlightened reply!

The other peripherals and processing tasks are relevant because they eliminate some of the ADC processing options.

I was hoping someone might have experience in >200KHz dual ADC small signal capture as I'd like to increase the resolution, which currently doesn't look possible due to local noise.  And yes, we have the usual VADC circuitry, ferrite beads, inductors, ground planes, etc.

[Piranha]

What ADC options other peripherals and processing tasks eliminate? Do they eat too much of the CPU processing power or is it something else?

Are you implementing software oversampling to increase the resolution? Some STM32 series can do it in a hardware. And some series have a 14/16-bit ADCs plus the oversampling feature.

Maybe the noise is actually a distortion because of an inadequate input driver circuit with a too high impedance?

You are avoiding the question of the driver impedance, an explanation of the 47 pF capacitor's purpose and the input circuit in general. If you actually want some helpful advice, you have to explain what you have, what is the goal and what is the issue stopping you. There is no fundamental difference in capturing 1 kHz or 384 kHz. The rules are the same, one just has to know and understand them.

[Robmar]

Haha, there is a vast difference between 1KHz capture and 385 KHz, i.e. DMA has to be used at the faster rate else the CPU cannot complete other tasks like FFT in time, extra noise generation at the higher rate, etc.  The 47pF is to suppress high frequencies and transients.

16-bit sampling is used, oversampling will not really yield any benefits.

Lets leave it there, unless you have something concrete to add.