ADC input resistance STM32C011J4M6
Hi everyone,
I am using the STM32C011J4M6 in the SO8N package.
I want to use the ADC on a low frequency signal (around 1kHz). My application needs to be very low power so I decided to put a big (around 100kOhms) input resistance on the ADC pin like we can see in the picture below.

The problem is that in the datasheet the maximum value of the resistance is 50kOhms.

I want to make sure that this maximum value is given only for one ADC clock frequency (35MHz in my case) and that if we lower the ADC frequency we can increase the Rain value. Am I right ? So if I use a 8MHz ADC clock, I can put a 100kOhms input resistance.
My second question is about the voltage drop across this resistance Rain. When the Cadc capacitor is charged there will be a current flowing into Rain, so there will be a voltage drop across it.
So my question is, when we increase Rain, we lower the input current in the ADC but we increase the voltage drop across Rain so we increase the error. Is it true ?
Best regards,
