ADC oversampling - how does this work exactly?

[Robmar]

In the RM the section on the hardware oversampling "25.4.31 Oversampler" is quite brief in it's explication, it states that "There are no changes for conversion timings in oversampled mode: the sample time is maintained equal during the whole oversampling sequence."

So it can oversample from 2x to 1024x, and it does what?, it takes extra samples in the set sample time, so that if we set say hadc1.Init.Oversampling.Ratio = 2, then it takes 2 samples in ADC_SAMPLETIME_1CYCLE_5 sample time for example, so our sample time halves?

So say the Ratio value is 2x, we set ADC_RIGHTBITSHIFT_1 to divide by 2.

And for 3x... there is no divide by 3, so I guess this works in powers of 2, ie. 2, 4, 8, 16, 32.... this is not stated in the RM.

Is this how it works?

[Chris21]

AN4629 Application note ADC hardware oversampling for microcontrollers of the STM32 L0 and L4 series

https://www.st.com/content/ccc/resource/technical/document/application_note/33/e1/e4/5c/aa/67/4c/74/DM00150423.pdf/files/DM00150423.pdf/jcr:content/translations/en.DM00150423.pdf

 

 

[Robmar]

Thanks, I've read those papers and to practical extents I'm not sure there's any useful info.

Using the DAC to add white noise isn't an option as the DAC is running audio, and there's no confirmation of the mechanism used by the H743 to achieve oversampling.

Do you know if it simply sub-samples within the current "clocks per sample" setting?

[Chris21]

 

 

Also: AN5537 How to use ADC Oversampling techniques to improve signal-to-noise ratio on
STM32 MCUs

https://www.st.com/content/ccc/resource/technical/document/application_note/group2/5f/8e/fb/19/fc/1e/48/4c/DM00722433/files/DM00722433.pdf/jcr:content/translations/en.DM00722433.pdf

Hardware oversampling feature overview
Note: This section concerns the STM32L4 series and information could slightly differ for other products. The dedicated documentation should be consulted.
The hardware oversampling engine accumulates the results of ADC conversions. The accumulated output data can be right-shifted (and rounded) to provide selected bit-depth in relation to OSR. The output value is not updated every sampling period, but once N samples are accumulated, therefore, the output data rate is
decimated by a factor of OSR.

The result is the average of accumulated samples as follows:
Result = 1
M ×
0
N − 1
Conversion tn (11)
Where both N and M can be adjusted:
• N is the oversampling ratio. It is set with the OVFS[2:0] bits in the ADC_CFGR2 register. It can be a factor
between 2x and 256x.
• M is the division coefficient (right bit shift). It is set with the OVSS[3:0] bits in the ADC_CFGR2 register. It
can allow to right shift the sum up to 8 bits.
In the case of STM32L4 series, the oversampling engine begins summing N samples. The sum is then right
shifted by M bits. The engine keeps the 16 least significant bits after the shift, and rounds the result to the nearest value according to the bits removed by the shifting.
The final result is saved in the ADC_DR data register and because of the 16-bit truncation, it cannot be
represented on more than 16 bits.

How to operate the bit-depth obtained with oversampling
When N samples of X bits are accumulated, the result can be coded on up to X + (ln(N) / ln(2)) bits.
For example, if the oversampling ratio N is 256x and the samples accumulated are on 12 bits, the sum of N terms will be on 20 bits since ln(256) / ln(2) = 8 and 12 + 8 = 20.
Next, the right shifting, which is up to 8 bits has to be taken into account.
Finally, the bit-depth is given by X + (ln(N) / ln(2)) – M but is limited to 16 bits because of the truncation.
Note: The number of bits X for a sample depends on the product used and can be found in its datasheet.
The Accumulate and average stage can be thought of as a kind of digital filter (often called accumulate-and-
dump). The frequency response of such filter is equivalent to a first order Cascaded-integrator-comb (CIC1)
Hogenauer filter. The frequency response in case of sampling frequency 1 MHz and OSR = 10 can be seen in Figure 13. Frequency response of accumulate-and-dump filter.

[Robmar]

I'd like to read something clear, like this for example, which I just wrote:-

"When oversampling is enabled, the number of oversamples selected are taken within the current sample time period and summed in a 26-but register. The summed value is then divided by the power of 2 division selected.  Take note that if the lowest clock count for sampling is used, only 2 sub-samples can be taken (that's how it looks from test results!)."

Is that correct?  There is no mention of the limits of the sub sampling as far as I can see, and clearly 1024x samples cannot be taken by the hardware without a very slow sample rate.

One thing that is clear is that the unwanted strong harmonic at +/- 45 KHz in the ADC samples disappears when oversampling is enabled.
ADC1 and ADC2 also have a DMA trigger 1500 times a second, this produces 2 harmonics of that frequency in the samples at a lower power level.  This seems to be power rail noise coupled, as when the event occurs, the activity spikes VDDA and no amount of decoupling has removed it entirely.