ADC3 data DMA transfer error

[sagit]

Hello members,

I have problem with functionality of DMA data stream for ADC3 peripheral. I have H743ZIT controller. ADC1 with DMA is fully and properly working for each channel. I have placed ADC data array to RAM_D2 section for ADC1. 

For ADC3 I have used RAM_D3 section which should be proper for BDMA implementation. ADC3 seems to work good - because I see changes in DR register, but DMA transfer error occur immediately after HAL_DMA_IRQHandler is executing. Exactly this case is true:

"else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))"

It leads to HAL_DMA_ERROR_TE error code.

 

In attachment you can see some files with config.

 

STM32CubeIDE

Version: 1.14.0

Build: 19471_20231121_1200 (UTC)

 

STM32CubeMX - STM32 Device Configuration Tool

Version: 6.10.0-RC9

Build: 20231120-2037 (UTC)

 

 

Thank you very much for help.

 

 

 

[TDK]

Probably the memory being accessed is not accessible by the (B)DMA. Can you show the relevant BDMA_Channel0 registers at the time of the error?

[sagit]

I hope this is what you are requesting.. Thank you very much.

[TDK]

Actually, I meant the registers themselves. If you pull up the SFRs window (Window -> Show View -> SFRs) when you're debugging, you can look at the register values directly.

That show's what's really going on at the chip level.

[sagit]

Thank you for your patience TDK.

Andrej

[TDK]

BDMA doesn't have access to 0x2400xxxx (AXI SRAM).

[KBéla.1]

Hello,

The solution of my problem is on the end of the post. I have found it, while I am writing the post. Maybe it is helpful for somebody.

I have the same DMA error, on mcu STM32H747 (Dual core CPU, actually M4 cpu is unused).

I am trying to run PDM Mic on STM32H747DISCO0 devel board, through SAI4 peripheral.

I am using the BSP example tutorial for STM32H747DISCO0, from STM32Cube_FW_H7_V1.11.1 library.

I have made some changes(e.g. LWIP has been added to project(with own .ld file), display part was removed)

So in file stm32h7xx_hal_dma.c, the next if is true.

 

 

/* Transfer Error Interrupt management **************************************/

else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U))

 

 

I have a defined  RAM_D3 memory part in FLASH.ld linker file. Line

 

RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K

 

And the variable for DMA memory is allocated, like: 

 

ALIGN_32BYTES (uint16_t recordPDMBuf[AUDIO_IN_PDM_BUFFER_SIZE]) __attribute__((section(".RAM_D3")));

 

But when I precompile the code Build analyzer shows me, that recordPDMBuf is not located in RAM_D3 memory, but it was still in RAM_D1.

Finally I have found a solution. I have added next line to my .ld file, and it is OK now:

 

.ARM.attributes 0 : { *(.ARM.attributes) }
.RAM_D3 : { *(.RAM_D3) } >RAM_D3
}

 

 

[LCE]

RM0433, page 103:

BDMA can only access SRAM4 in domain D3.

I love this numbering logic of ST... :grinning_face_with_sweat:

On a H723/735 DMA1 and DMA2 can also access ADC3, but has more SRAM options.

[sagit]

I would like to thank you all very much. We managed to get it up and running. Thanks to an insight from TDK, it was evident that the address pointing to the variable's location was different from where it should have been. The problem was resolved by adding a missing section to the linker. Now it is correct. I am somewhat surprised that the compiler did not identify any problem when setting an attribute that doesn't exist. But once again, thank you for your help.

 

Andrej