APMemory APS12808 OSPI memory connection to STM32H723ZGT6

[Maxim357]

Hello,

I am writing to seek advice on connecting an APMemory APS12808 OSPI memory to the STM32H723ZGT6 microcontroller.

Initially, I attempted to adapt the code from this thread ( https://community.st.com/t5/stm32-mcus-products/stm32h7-octospi-mode-hyperbus-hyperram-access-and-delay-block/td-p/143237/page/2 )  from @Alex - APMemory  to the STM32H723ZGT6. You can find the result in the attached file `main_1.c`. With this configuration, read and write operations do work, but I am encountering issues with data mismatches/corruption.

Subsequently, I tried to enable the Memory Mapped mode based on Application Note AN5050. This is where significant problems began I cannot get this mode to activate. The relevant code is in the attached file `main_2.c`.

My specific questions are:

1. Is there a known working example for enabling the Memory Mapped mode for this type of memory?

2. Why does AN5050 not cover the MR (Mode Register) configuration and memory initialization sequence?

3. Is there any functional difference in which OCTOSPI interface (OCTOSPI1 or OCTOSPI2) is used to connect the memory?

4. Is it acceptable to leave the memory's RESET pin unconnected (floating) if it is not being used?

5. Can I use pins with different Alternate Function (AF) numbers within the same OCTOSPI connection (e.g., for data lines), or must they all belong to the same predefined AF group?

6. There is a dedicated driver available here: ( https://github.com/STMicroelectronics/stm32-aps6408 ). How current and reliable is this driver? Are there any usage examples available?

7. In this thread ( https://community.st.com/t5/stm32-mcus-products/unable-to-read-reset-values-of-the-stm32h730vb-octospim/td-p/212094 ), I read about the OCTOSPIM clock being disabled by default. Is this issue still relevant for the STM32H7 series, and are any specific actions required to ensure proper memory operation?

8. On one of my PCB revisions, the memory's B1 pin is accidentally tied to ground. Is this configuration acceptable, or will it prevent the memory from functioning correctly?

Thank you for your assistance.

Best regards, Max

[KDJEM.1]

Hello @Maxim357 and welcome to the community,

 

You can find OSPI_PSRAM_MemoryMapped example in STM32CubeU5. This example based on APS6408L APMemory memory and describes how to write and read data in memory-mapped mode in an OSPI PSRAM memory and compare the result. I recommend you to take a look at this example and get inspired.

There is no functional difference in which OCTOSPI interface connected to the memory, you can use OCTOSPI1 or OCTOSPI2.

For the OCTOSPIM clock, the issue is solved in STM32CubeMX.

 /* Peripheral clock enable */
 __HAL_RCC_OCTOSPIM_CLK_ENABLE();
 __HAL_RCC_OSPI1_CLK_ENABLE();

8. On one of my PCB revisions, the memory's B1 pin is accidentally tied to ground. Is this configuration acceptable, or will it prevent the memory from functioning correctly?

Are you asking about PB1?

Thank you.

Kaouthar

[Maxim357]

Hello,
Thank you for your answer.
Thank you, I will make sure to check out that example.
I was referring to the B1 pin on the memory module itself. I have seen
APMemory employees here on the forum; perhaps they can provide some insight.

[Alex - APMemory]

4. Is it acceptable to leave the memory's RESET pin unconnected (floating) if it is not being used?
      => No issue
8. On one of my PCB revisions, the memory's B1 pin is accidentally tied to ground. Is this configuration acceptable, or will it prevent the memory from functioning correctly?

   => No issue

Alex

[KDJEM.1]

Hello @Maxim357 ;

 

Could you please share the memory datasheet?

 

Thank you.

Kaouthar

[Maxim357]

I have ported the code from the link for the H723 but encountered an error.

When calling the function HAL_OSPI_Receive(Ctx, Value, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) , an error occurs in the file stm32h7xx_hal_ospi.c at the following lines:

• *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr;

• hospi->pBuffPtr++;

• 

I am also attaching the memory datasheet.

 

Thank you.

[Tesla DeLorean]

The disassembly doesn't look viable for sure. Not sure it the core has locked out access, or the pod is not connecting. So not sure stopping or stepping here is productive at this point.

I'd also caution on placing a peripheral watch view, as this tends to interfere with the operation of FIFO and stateful registers. Add some app side dumping or telemetry if possible.

You can inspect RAM based peripheral instance structures.

For Hard Fault situations.

https://github.com/cturvey/RandomNinjaChef/blob/main/KeilHardFault.c

 

[Maxim357]

Thank you for your answer; it helped me make progress.

The code execution advanced further after I disabled the System Viewer window. However, it now gets stuck while comparing the values of the MR0 and MR8 registers.

Does this information from the debugger indicate a real issue, or could it just be a debugging artifact?

Furthermore, could displaying the MR register values in the Call Stack and Locals windows somehow be influencing their actual values?

[Maxim357]

Good afternoon,

I have successfully established communication with the memory and performed a basic write-read test operation.

However, the Mode Register (MR) values still do not fully match the expected values, even though operations seem to be proceeding.

Could you please advise on the correct way to determine the proper MR values?

Furthermore, I purchased a Wio Lite AI board and realized there might be issues with my own board's design.

I have two reference designs: one from the MB1242 and another from the Wio Lite AI.

In both of these designs, the RESET pin is connected to VDD.

What is the purpose of this?

Is it necessary to add a series resistor and a capacitor to ground on the CLK line?

Doesn't this overcomplicate the design?

Should the Chip Enable (CE) pin be pulled up to the power supply via a resistor?

Is a 10μF capacitor in the power supply circuit a good idea?

Why are pins A2 and A5 connected to the power supply circuit in the MB1242 design?

 

Maxim

[ccuebler]

Hi @Maxim357 
I use two of them in OSPI multiplexed mode.
If You not have any HW issue ( wiring problems ) try with these settings:

OSPI module's clock : 160MHz
OSPI prescaler: 2 (  PSRAMs running in 80MHz)
Refresh : 640
ChipSelectBoundary: 10 

Memory Mapped mode Read Dummy : 8, DQS Enable, All DTR Enable
Memory Mapped mode Write Dummy : 4, DQS Enable, All DTR Enable

Register read Dummy: 6, DQS Enable, ADDR + Data DTR Enable
Register Write Dummy : 0, DQS Disable, ADDR + Data DTR Enable

MR0: 0x2C // Fix Latency, Latency code: 6
MR8: 0x0B // 1K Byte Wrap with boundary crossing

I hope it helps You!

Krisztian