Ask about the use of STM32U57XX MPU

[YunYang]

Hi， the platform is STM32U57X

Question:

1. The variable is in the non secure area of SRAM.
   Why can't variable A in SRAM1 and variable B in SRAM2 assign values to each other after turning on MPU, otherwise it will trigger a hardware exception interrupt.
2. Do you have any modification suggestions or tips for the following code?

 // Configure MPU regions
 MPU_Region_InitTypeDef MPU_InitStruct = {
 .Enable = MPU_REGION_ENABLE,
 .Number = MPU_REGION_NUMBER0,
 .BaseAddress = SRAM1_BASE_NS,
 .LimitAddress = SRAM1_BASE_NS + (192 * 1024 - 1),
 .AttributesIndex = MPU_ATTRIBUTES_NUMBER0,
 .AccessPermission = MPU_REGION_ALL_RW,
 .DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE,
 .IsShareable = MPU_ACCESS_NOT_SHAREABLE,
 };
 HAL_MPU_ConfigRegion(&MPU_InitStruct);

 MPU_InitStruct.Number = MPU_REGION_NUMBER1;
 MPU_InitStruct.BaseAddress = SRAM2_BASE_NS;
 MPU_InitStruct.LimitAddress = SRAM2_BASE_NS + (64 * 1024 - 1);
 HAL_MPU_ConfigRegion(&MPU_InitStruct);

 MPU_InitStruct.Number = MPU_REGION_NUMBER2;
 MPU_InitStruct.BaseAddress = SRAM3_BASE_NS;
 MPU_InitStruct.LimitAddress = SRAM3_BASE_NS + (512 * 1024 - 1);
 HAL_MPU_ConfigRegion(&MPU_InitStruct);

 MPU_InitStruct.Number = MPU_REGION_NUMBER3;
 MPU_InitStruct.BaseAddress = SRAM4_BASE_NS;
 MPU_InitStruct.LimitAddress = SRAM4_BASE_NS + (16 * 1024 - 1);
 HAL_MPU_ConfigRegion(&MPU_InitStruct);

 // Configure MPU memory attributes
 MPU_Attributes_InitTypeDef MPU_AttributesInit = {
 .Number = MPU_REGION_NUMBER0,
 .Attributes = MPU_DEVICE_nGnRnE | MPU_WRITE_THROUGH | MPU_TRANSIENT | MPU_NO_ALLOCATE,
 };
 HAL_MPU_ConfigMemoryAttributes(&MPU_AttributesInit);

 MPU_AttributesInit.Number = MPU_REGION_NUMBER1;
 HAL_MPU_ConfigMemoryAttributes(&MPU_AttributesInit);

 MPU_AttributesInit.Number = MPU_REGION_NUMBER2;
 HAL_MPU_ConfigMemoryAttributes(&MPU_AttributesInit);

 MPU_AttributesInit.Number = MPU_REGION_NUMBER3;
 HAL_MPU_ConfigMemoryAttributes(&MPU_AttributesInit);

 // Enable the MPU
 HAL_MPU_Enable(MPU_HFNMI_PRIVDEF);

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#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */
#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */
#define SRAM3_BASE_NS (0x20040000UL) /*!< SRAM3 (512 KB) non-secure base address */
#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */