Backup domain is not reset by setting RCC_BDCR.BDRST, unless PWR_CR.DBP is set, too

[waclawek.jan]

In an STM32F427, according to the Backup domain reset subchapter of RCC chapter of RM0090rev.19, backup domain can be reset by setting RCC_BDCR.BDRST. There is no other condition to this mentioned in that subchapter nor elsewhere in related material (e.g. in description of RCC_BDCR.BDRST bit) in the RM.

However, experimentally I found, that backup domain reset does not happen after setting RCC_BDCR.BDRST, if PWR_CR.DBP is not set.

JW

[Imen.D]

Hello @Community member​ ,

Yes, DBP bit is to disable backup protection, the backup won’t be write accessed without setting DBP same for the BDRST.

This is mentioned in the RM, in the "Backup domain access" part :

Imen

[waclawek.jan]

Hi Imen,

The RCC_BDCR.BDRST bit is *not* in the backup domain, as proven by the ability to write into it and read it back without setting PWR_CR.DBP. So why would any text on Backup domain access pertain to that bit?

The description of RCC_BDCR explicitly states the bits which are protected by PWR_CR.DBP and RCC_BDCR.BDRST does not belong to them.

> This is mentioned in the RM, in the "Backup domain access" part :

No, that text does not mention backup domain *reset*, nor RCC_BDCR.BDRST bit. There is NO mention of the need to enable backup domain access for the backup domain reset.

Contrary, there is an explicit chapter dealing with backup domain reset, and it fails to mention PWR_CR.DBP:

 

I fail to see why the ST manuals expect users being clairvoyants. How hard it may be to properly describe features and procedures?

JW

@Imen DAHMEN​ 

[Imen.D]

Hi @Community member​,

Your feedback is important and clear now.

I've highlighted an internal request to the involved people to take a closer look at this and take the necessary actions.

Thank you for noticing this and for helping to improve the ST documentation! :smiling_face_with_smiling_eyes:

Imen

[Piranha]

By the way, I looked into RM of F7 and L4 and it's the same there. So probably RM of all series must be checked for this issue. :)

[waclawek.jan]

Thanks, Imen.

Jan