BOOSTEN / BOOSTRDY doesn't seem to be working on STM32U575

[ShawnP]

STM32u575 reference mannual indicates that PWR->VOSR BOOSTEN must be set and PWR->VSOR BOOSTRDY must be set by hardware before clocks are raised past 55MH.

 

using this code to try and accomplish that:

	// set boost enable to support clocks above 55MHZand wait for BOOSTRDY
	MODIFY_REG(PWR->VOSR, PWR_VOSR_BOOSTEN, PWR_VOSR_BOOSTEN);
	while (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) != PWR_VOSR_BOOSTRDY) {}

I see BOOSTEN getting set but loop hangs and BOOSTRDY is never set by hardware.

Is there some other item that need to be configured for this to work?

All assistance approciated.

 

Shawn

 

[ShawnP]

Addendum - it's strange that I don't see the sample applications setting BOOSTEN yet having no difficulting running at 160MHZ...

 

Puzzling....

[ShawnP]

2nd addendum - 

seems that the BOOSTRDY bit does not come on until after I've enabled MSIS and set the PLL1 source to MSI.

Not sure if there are other ways that BOOSTRDY will get activated.

Also, the example I'm using for testing is an LL example RCC_UseHSI_PLLasSystemClock.  out of the box, this example never sets BOOSTEN and runs fine at 160MHZ.  I watch the VSOR register in debug while the application is running and BOOSTEN and BOOSTRDY are never set.

The only way I got BOOSTRDY to trigger in this application is adding code to set BOOSTEN prior to running SystemClock_Config().  When I do this I can see the BOOSTEN flag getting set in the debugger but the BOOSTRDY bit does not get set until after MSIS is enabled and RCC->PLL1CFGR is configured with MSI as the source.

[AScha.3]

So whats your Vdda level ?

[waclawek.jan]

@AScha.3,

that's  a different booster, for the analog switches.

What @ShawnP talks about is what the RM calls EPOD booster, needed to achieve higher system clocks.

JW

[ShawnP]

---

@waclawek.jan wrote:

@AScha.3,

that's  a different booster, for the analog switches.

What @ShawnP talks about is what the RM calls EPOD booster, needed to achieve higher system clocks.

JW

---

that is correct!

further question / observation:

Reference manual documentation is very confusing on both the purpose of the VOSR_BOOSTEN field and the associated PLL1MBOOST field in PLL1CFGR register.

The field is labled "PLL1MBOOST " yet the values of the field indicate the input source frequecy is being reduced by division (1/1 to 1/16) by even numbers (except 1).

In addition, in the same register, "PLL1CFGR", the "PLL1M" field is the "prescaler" in front of the multiplier.  As an asside, the multiplier value is configured with the PLL1DIVR PLL1N field - how confusing is that?

So now I have two fields that seem to divide down the source clock before it enters the multiplication stage.   Do these fields compound each other?  Does one replace the other when PLL1MBOOST is enabled?  Both fields have values between 1 and 16.

All in all I'm still very confused about how all this is supposed to work and I suspect I'll only know by doing exhaustive experimentation - which theoretically the reference manual should prevent us from needing to do.

Anyone know how all this works?  Or even better, knows a source of clear and accurate documentation?

Shawn

 

. 

[ShawnP]

Ha - might have answered my own question - here's my interaction with ChatGPT:

If this is correct it's really kind of amazing!!!

[waclawek.jan]

Why do you think ChatGPT "knows" more than what's in the RM?

Anything else is ChatGPT's hallucination. I though this is pretty clear by this point.

Instead, at this point, you should contact ST directly, through FAE or the web support form.

JW

[ShawnP]

Well perhaps I'm just not yet good at digging the information above out of the reference manual.

 

Perhaps you could show me where in the reference manual it specifically says that when you set BOOSTEN that the chip switches from using the values in PLL1M and uses the values in PLL1BOOST instead.   It might be there but after hours of searching I turned to this forum - and got no answers.

 

I'd be happy to be schooled on better approaches to get the answers I need than coming to this forum.

 

Any tutoring from the wise "guru" would be welcome.

[waclawek.jan]

The description in RM is not adequate to fully understand the purpose and function of  this "boost" and what the RM calles EPOD (and DS does not mention them at all).

I don't use the 'U5 nor am I an ST insider to be able to shed more light on this topic. That's why I've recommend you to contact ST directly.

JW

 

[Sarra.S]

Hello @ShawnP 

In the section 10.5.4 Dynamic voltage scaling management you will find the required sequence to use the EPOD (embedded power distribution) booster , indeed it is mandatory to follow it.

>>the BOOSTRDY bit does not get set until after MSIS is enabled

I think it is not mandatory that the PLL source is MSI, it can also be HSI or HSE, but PLL must be enabled with clock selected as explained in the sequence.

>>it's strange that I don't see the sample applications setting BOOSTEN yet having no difficulting running at 160MHZ...

the fact that they are running properly does not mean it will always work properly. When increasing the frequency, the consumption of all logic supplied by VCORE increases, and the consumption depends on the number of enabled peripherals, their frequency, the process and the temperature.

The behavior above 55 MHz, whatever enabled peripherals and PVT conditions  are only  guaranteed if Booster is enabled. It does not mean that it cannot work in typical conditions, but it is not guaranteed.

>>Regarding your question about PLL dividers; 

The booster needs a clock between 4 and 16 MHz, as explained in 10.5.4 Dynamic voltage scaling management . PLL1MBOOST divider is only used to generate the booster clock at required frequency. There is no link with the PLL1 division and multiplication factors. The PLL input clock is used because we are sure that the PLL is already used when frequency is increased above 55 MHz, so we can reuse the PLL input source selection instead of another source selection just for the booster.

I hope that makes things a bit clearer!