Boot in dualcore micro

[GMene.785]

Hello everyone,

I'm seeking guidance on creating a custom dual-core boot using only an external flash.

Previously, I managed to accomplish this for a single-core microcontroller, with the bootloader residing in the internal flash while other code (main application and TGFX images) were stored on an external flash. We also developed a custom OTA system, but currently, we're only using one .bin file to update our devices.

1. How should I configure both .id files for the individual cores?
2. In order to transition to the application, do I need to first jump to one of the cores and then initialize the other? Or is there an alternative method?
3. Are there any documents or example codes available for this particular scenario?

4. I will always have two .bin files, or I can merge both?

I appreciate any assistance or pointers you can provide. Thank you!

[FBL]

Hello @GMene.785 

 

1. First, I suggest taking a look at the H7 dual core system architecture STM32H745/755 and STM32H747/757 lines dual-core architecture - Application note. You need to determine the memory regions and entry points for each core. You can check the examples provided in Cube.

2. You can run separately the cores. But, if you need to synchronize between them, you can use IPC mechanism and shared resources including inter-processor communication using OpenAMP and FreeRTOS message buffer or using HW semaphore. STM32H745/755 and STM32H747/757 lines inter-processor communications - Application note

3. Could you explain why merging two binaries then jump to one user-application execution from one external memory.

[GMene.785]

I will go further on details, maybe you can help me.

 

On a microcontroller with one core and QuadSPI, the internal memory region is at 0x08000000 and the QuadSPI at 0x90000000. I have two firmwares, one for my own bootloader and one for the application, the Bootloader is in the internal flash region (0x08000000) and the application firmware in the QuadSPI region (0x90000000), changing the project's .id files. When the Bootloader updates the application, it changes the QSPI data, I place the QSPi in the memorymap, and then give a JUMP (the interrupt vector I give an OFFSET to the QSPI). This works well, I have products like this.

micro memory organization with one core:
MEMORY
{
DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 1024K
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
OSPI (xrw) : ORIGIN = 0x90000000, LENGTH = 64M
}

On the dual core microcontroller, I have the M4 in region 0x08100000 and the M7 core in region 0x08000000, how should I organize them in the QSPI in the application firmware? 0x90000000 and 0x90100000? ( I don't think so).

micro memory organization with dual core:
CORE M7:
MEMORY
{
RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K /* Memory is divided. Actual start is 0x08000000 and actual length is 2048K */
DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
QUADSPI (r) : ORIGIN = 0x90000000, LENGTH = 64M
SDRAM (xrw) : ORIGIN = 0xD0000000, LENGTH = 6144K
SDRAM2 (xrw) : ORIGIN = 0xD05DC000, LENGTH = 2048K
}

CORE M4:
MEMORY
{
FLASH (rx) : ORIGIN = 0x08100000, LENGTH = 1024K
RAM (xrw) : ORIGIN = 0x10000000, LENGTH = 288K
}

 When I compile the dual core firmware, two hex. files are generated, one for each CORE. I need to have two bootloaders and will both give JUMP to their memory region on the QSPI?

Is there any example of a dual core microcontroller with bootloader?

[Tesla DeLorean]

I probably would avoid having two binaries, best to package both in a single wrapper to manage size, integrity and slack space between the two in memory if you have them at two different bank boundaries.

The FLASH is dual-ported, but still probably want to avoid any conflicts or contention