Hi @Snaku,
No, this area (high-cycle data flash) will be disabled if EDATA1_EN and EDATA2_EN are set to 0.
In this case, the entire flash memory is used for executable code, accessible at the standard address around 0x0800_0000.
However, if the high-cycle data flash area is enabled (EDATAx_EN = 1), this area is then remapped to a different address range (typically 0x0900_0000), separate from the code area, to prevent the CPU from executing code in the data flash region., let me explain in detail:
By default, the entire flash memory is used to store executable code, accessible at the standard address starting around 0x0800_0000.
This code area features a 9-bit ECC for every 128 bits of data, and each sector is 8 kB in size.
The microcontroller allows configuring a portion of the flash as a high-speed data flash region, dedicated to data storage with high endurance (up to 100,000 erase cycles).
This region is mapped to a different address range, around 0x0900_0000, and uses a different ECC scheme (6 bits for every 16 bits of data) with smaller sectors of 6 kB.
This configuration is enabled via the EDATA1_EN and EDATA2_EN bits in the User Option Bytes, along with the EDATA1_STRT and EDATA2_STRT thresholds that define the start of this region within each bank.
If both EDATA1_EN and EDATA2_EN are set to 0, the high-speed data flash region is not enabled, so the entire flash is available for code in the 0x0800_0000 range.
If you enable the data flash region (EDATAx_EN = 1), part of the flash is reserved for data storage in the 0x0900_0000 range, and you should not place executable code there.
Thank you.
ELABI.1