Clarification on Debug Register Configuration in STM32H755

[wukong]

Hi,

I'm working with the NUCLEO-H755ZI-Q, which features dual cores (Cortex-M4 & Cortex-M7). I’m trying to understand whether these two cores have separate debug registers, such as DHCSR (Debug Halting Control and Status Register).

I have reviewed RM0399 and the Armv7-M Architecture Reference Manual, but I couldn't find a definitive answer. To investigate further, I attempted to access DHCSR (0xE000EDF0) on AP0 and AP3 using STM32CubeProgrammer, and I observed that both cores displayed the same value. However, when running a project in STM32CubeIDE, where I separately access DHCSR on M4 and M7, I see different values for each core.

This discrepancy has left me confused about the debug register configuration on STM32H755. Do Cortex-M4 and Cortex-M7 maintain independent debug registers, or are they shared?

Any insights or official documentation references would be greatly appreciated!

[TDK]

Each core has its own debug registers. The DHCSR register and other debug registers are part of the Cortex core.

[wukong]

Thank you for your help! Is there any manual or example that supports this?

[wukong]

Assuming that each core maintains its own set of debug registers, how do the M4 and M7 cores get different values ​​when accessing the same physical address 0xE000EDF0?

[Tesla DeLorean]

The two core have independent address spaces. They dual-port some common RAM and FLASH regions, and access to the peripherals.

The debug registers are unique to each Cortex-Mx core.

ARM has technical manuals. ST has the Programming Manuals (PM) which cover the debug registers to an extent.

Perhaps also check the Reference Manual (RM) to better understand the internal connectivity and the bus relationships with the cores, memory and peripherals .

[wukong]

I read about Memory and bus architecture, and found that addresses above 0xDFFFFFFF are reserved, so I can't tell from that. But the "Programming Manuals (PM)" you mentioned inspired me. I haven't paid attention to this material before, and I will look for it and learn from it. Thanks!

 

[TDK]

Not sure anything spells it out explicitly.

You can see the ARM documentation to see that DHCSR is part of the M7 and M4 cores, just like a bunch of other things like registers, VTOR, etc. There are two cores on the chip. I think it's up to you to connect the dots.

> Assuming that each core maintains its own set of debug registers, how do the M4 and M7 cores get different values ​​when accessing the same physical address 0xE000EDF0?

When you debug the chip, you connect to an access point which is connected to a core. Here, either AP0 (M7) or AP3 (M4). When you ask for data at an address, it gets what is mapped at that address for that core. They share much of the same mapping (like SRAM) but not everything. Core registers are core-specific.

 

SCB->CPUID on M7 core (AP0):

 

SCB->CPUID on M4 core (AP3):

 

[wukong]

I think you are right. Yesterday I checked the Arm®v7-M Architecture Reference Manual and found the CPUID base register. After accessing it through stm32cubeprogrammer, I got the same value as you.

 

[wukong]

Since debug registers are core-specific, accessing a debug register requires reading the CPUID base register, which is read-only and restricted to privileged access.

Now, I'm wondering if there are any methods that allow one core to read/write another core's debug registers (e.g., DHCSR).

Any insights or suggestions would be greatly appreciated!

[TDK]

> Now, I'm wondering if there are any methods that allow one core to read/write another core's debug registers (e.g., DHCSR).

No, a core does not have access to data internal to another core.

[wukong]

Copy that, thanks