Clarification on SPI6 Peripheral Clock Domain in STM32H747I

[SaiGaneshCS]

Hello,

I am working with the STM32H747I microcontroller and using the SPI6 peripheral to interface with an external ADC (MCP3462RT).

I have observed that when the system clock (SYSCLK) is set to 120 MHz, SPI6 communication works correctly and the ADC provides valid data. However, when SYSCLK is configured to 480 MHz, the ADC starts giving wrong readings even though SPI6 does not hang.

To debug this further, I need clarification:

1. On the STM32H747BIT6, is SPI6 clocked from APB4 (via RCC_APB4ENR) or from another APB domain?

2. If SPI6 is indeed on APB4, does its effective clock depend on D2PCLK1/D2PCLK2 or directly on D3PCLK4?

3. Are there any known limitations when running SPI6 at high system clock frequencies (SYSCLK = 480 MHz)?

Understanding the exact clock domain of SPI6 will help me tune the prescaler and ensure reliable ADC communication.

Thanks in advance for your support.

Best regards,
Sai Ganesh CS

[TDK]

PCLK4 is here in the clock tree and depends on everything directly upstream of that node.

It doesn't depend on D1PPRE or D2PPREx.

[Amel NASRI]

Hi @SaiGaneshCS ,

SPI6 is mapped to APB4 and the maximum APB4 clock frequency is 120 MHz.
If SYSCLK is 480 MHz, you must set APB4 prescaler to divide by at least 4 to keep APB4 ≤ 120 MHz.
Depending on SPI mode and your operating conditions, you need to be aligned with max SPI clock frequency as specified in product datasheet (see "SPI interface characteristics" section).

-Amel