Configuring DQS Delay for OctalFlash on STM32U5A9J-DK.

[sohm]

Hello STM Community,

I am currently working on the STM32U5A9J-DK board and interfacing with an OctalFlash memory. I need assistance in optimizing the data capture process using the DQS (Data Strobe) signal.

In my setup, the OctalFlash sends both DQS and DQ signals at the same time, and the SoC needs to apply a ¼ clock cycle delay to the DQS signal to achieve the best setup and hold times for reliable data capture. I want to adjust this delay and evaluate its impact on the data eye to ensure proper signal integrity.

Does anyone have experience with this on the STM32U5A9J-DK? Are there any specific examples available or any other documentation that demonstrate how to configure the DQS delay for the Octal SPI interface?

Any insights, code examples, or documentation references would be greatly appreciated!

Thank you in advance for your help.

[KDJEM.1]

Hello @sohm ,

 

--Configuring DQS Delay

Do you mean delay block?

The delay block is an independent peripheral integrated inside the STM32 MCU that can be configured for the external serial memory controllers in order to fine tune the data-received sampling clock. Its role is also to apply a phase-shift to the clock or DQS signal when reading from external memory.

For more information about the delay block configuration, I advise you to take a look at AN5050 section 6 OCTOSPI and HSPI/XSPI interface calibration process.

Also you can find an example DLYB_OSPI_NOR_FastTuning has been tested with STMicroelectronics STM32U575I-EV (MB1550) board and can be easily tailored to any other supported device and development board.

May this discussion can help you for delay block calibration with STM32U5A9J-DK board

 

Please let me know if your request is answered or not?

Thank you.

Kaouthar

 

[sohm]

Hello,

Thank you for the detailed response. I’m specifically trying to understand how to configure the HAL_OSPI_DLYB_SetConfig API for a ¼ cycle delay on the STM32U5A9J-DK board.

For example, if my OSPI clock is set to 125 MHz:

• Clock period = 8 ns
• ¼ cycle delay = 2 ns

I would like to know how to calculate the Struct.Units and Struct.PhaseSel values.

I understand that Units is used to define the delay within the 256 divisions of the clock period, and PhaseSel further fine-tunes the delay.

In this case:

1. How do I determine the correct Units and PhaseSel values for a 2 ns (¼ cycle) delay?
2. If the clock is divided into 256 units, is my calculation for Units = (2 ns / 8 ns) × 256 = 64 correct?
3. What should be the PhaseSel value?

Thanks again for your guidance.

 

[KDJEM.1]

Hello @sohm ,

 

STM32CubeMX does not configure or generate code for delay block. The HAL_OSPI_DLYB_Cfg_Struct.Units and the HAL_OSPI_DLYB_Cfg_Struct.PhaseSel are only the initial value.

So, UNIT[6:0]: Delay of a unit delay cell is calculated with this formula Unit delay = initial delay + UNIT[6:0] x delay step. And, SEL[3:0]: Phase for the output clock is calculated with this formula Output clock phase = input clock + SEL[3:0] x unit delay.

With unit delay and initial delay are mentioned in the datasheet.

 In order to correctly configure the delay block with the OCTOSPI, you could refer to the examples proposed in the STM32CubeFWU5 and consult section "32 Delay block (DLYB)" in the RM0456 for more details about the delay block. Example1: STM32Cube_FW_U5_V1.5.0\Projects\STM32U575I-EV\Examples\DLYB\DLYB_OSPI_NOR_FastTuning and Example2: STM32Cube_FW_U5_V1.5.0\Projects\B-U585I-IOT02A\Examples\DLYB\DLYB_OSPI_PSRAM_ExhaustiveTuning.

Also, you can check the UNIT and SEL values after configuration using SFR options using STM32CubeIDE under DLYB_CFGR register.

Is my reply answer your request?

Thank you.

Kaouthar

 

[sohm]

Hello @KDJEM.1 

Thank you so much for the clarification. I wanted to understand this better with an example, if you can please check and clarify whether my understanding is correct or not. As I am working with the STM32U5A9J-DK board, specifically interfacing with an OctalFlash memory. My goal is to configure a ¼ clock cycle delay for the DQS signal to ensure reliable data capture.

Based on the details provided, I am using the following parameters as an example:

• Clock frequency: 125 MHz, resulting in a clock period of 8 ns.
• Required delay: ¼ clock cycle = 2 ns (2000 ps).

From the datasheet of STM32U5A9J-DK board, I have the following information:

• Initial delay (tinit): Typical = 1300 ps (min = 900 ps, max = 2100 ps).
• Unit delay: Typical = 41 ps (min = 34 ps, max = 51 ps).

Using the formula provided:

• Unit delay = Initial delay + UNIT[6:0] × delay step.
• Phase for output clock = Input clock + PhaseSel[3:0] × unit delay.

My calculation:

1. Total delay needed: 2000 ps.
2. Delay to achieve using UNITs = 2000 ps – Initial delay (1300 ps) = 700 ps.
3. UNIT calculation: 700 ps ÷ 41 ps/unit ≈ 17.

Therefore, I have to set UNIT = 17

 

For fine-tuning, I plan to use PhaseSel for additional delay. Assuming the typical unit delay is 41 ps, setting PhaseSel = 1 or 2 could provide an additional 41-82 ps of delay if needed.

 

HAL_OSPI_DLYB_Cfg_Struct.Units = 17;

HAL_OSPI_DLYB_Cfg_Struct.PhaseSe = 1;

HAL_OSPI_DLYB_SetConfig(&hospi1, &HAL_OSPI_DLYB_Cfg_Struct);

My Question:

Is this calculation correct based on the formula provided in the HAL_OSPI_DLYB_SetConfig API and the information from the datasheet? I would like to understand if this approach is valid for setting the ¼ cycle delay.

Thank you for your assistance!

[KDJEM.1]

Hello @sohm ,

 

Thank you for sharing this calculation.

The parameters given in Table 148. Delay block characteristics are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 33. 

Also, it mentioned in the table three values min, typical and max.

I think, you can used this as initial values.

 

 

HAL_OSPI_DLYB_Cfg_Struct.Units = 17;

HAL_OSPI_DLYB_Cfg_Struct.PhaseSe = 1;

HAL_OSPI_DLYB_SetConfig(&hospi1, &HAL_OSPI_DLYB_Cfg_Struct);

 

 

Please see this training for delay block procedure.

Note: The analog part of the delay block (the delay line) is PVT dependent, which requires the application to retune and recenter the output clock phase shifting if the STM32 VCORE voltage scaling or the environmental temperature change.

Thank you.

Kaouthar

[sohm]

Hi @KDJEM.1 

 

Thank you for the clarification and guidance regarding the delay block characteristics!

As a summery I believe my calculation is correct to determine the delay unit and phasesel value.

Based on the data provided in Table 148 for initial values, I believe it is possible to achieve the DQS delay by 1/4 cycle through configuring the delay block. 

 

Thank You

[KDJEM.1]

Hello @sohm ,

 

Could you please click on Accept as Solution on the reply which solved your issue or answered your initial request.

If you have any question and/or you need clarification or support, please don't hesitate to create a new post in STCommunity.

Thank you for your contribution in STCommunity.

 

Kaouthar