Confusion about ICACHE errata on the STM32U575

[jmitchell]

The errata for the STM32U575 series includes the following:

 

We would like to use the first option of the 2 listed workarounds (the one that does NOT require disabling and reenabling the ICACHE).  Does ST have any implementation examples of this workaround?

 

I am confused about why it is necessary to put the low-power entry code in a non-cacheable region.  We use a WFI instruction to put the MCU into STOP mode.  If we could ensure that the WFI was in the last 2 bytes of a 16-byte block of memory, would that fix the errata?  This way, the next instruction after WFI (and thus the 1st instruction executed outside of STOP mode) would be guaranteed to be in the next cache line.  In that case, would the WFI and preceding code need to be in a non-cacheable region?

 

Thanks!

[Sarra.S]

Hello @jmitchell, 

I have submitted this question to the dedicated team (Internal ticket number: Ticket 215360) 

I will keep you updated! 

[Sarra.S]

Hi again @jmitchell, 

To make the entry code non-cacheable, identify its address from the map file and configure the MPU to disable caching for that range. For a more robust approach, placing the code in a dedicated non-cacheable section is recommended.
For data, just access a different memory location right after the WFI instruction, ensuring execution occurs after wakeup.

Hope that helps!