Confusion about VCO input frequency "the recommended input frequency of 2MHz"

[1f333]

What's up with the recommended 2MHz ? 

Im looking at F4 & F7 series...

So 2MHz are recommended for VCOin (reference manual e.g 0410, RCC_PLLCFGR -> PLLM), but every Cube Example seems to be giving 1MHz to the VCOin.

Even in datasheet (DS11532 Rev 8, Table 47. Main PLL characteristics ) typical value for f pll_in is 1.

How this recommendation should be treated? Is it some kind of bad joke? Or some copy-paste error?

Wouldn't be the first time reference manual is incorrect> just check apb1 & apb2 max frequency values(rm0410)

What are the advantages / use cases / benefits when using 1MHz instead of 2?

[STOne-32]

Dear @1f333 ,

 

That’s great question ! Thank you for asking it. To go straight to the point : Having PLL input at 1MHz is very simple to all computation after , as very easy to have the M factor and reach any VCO and system clock . 1 * xx ( maths) also the same for any integer HSE / Crystal ( most used ) either an even value or odd value . We can transform that value to 1 easily such as 8MHz, 25MHz etc it is always an integer value .  So I would say 99% of engineers / software / developers will use 1MHz as starting point .  Now, I confirm that using 2MHz is better and recommended for best VCO PLL loop - less jitter and stability- lower then the value put in datasheet in case to reach higher Frequency as the divider after VCO wil be lower .  To see it it would very difficult but is my recommendation too if your application is sensitive to that requirement.

Hope it helps you .

Ciao

STOne-32

[1f333]

Thank you for replying quickly. I've already thought that having simpler maths x1 /1 would be the main reason for ignoring some recommendations... Well, guess im the 1% chosing 2mhz as starting point, when playing around with f4 & f7 devices.

But then, a WB55 comes along, which has a HSE prescaler and VCO In in range of 2.66..16MHz.

Would here be better to pick higher value for PLL input, in order to have lower PLL jitter? Currently i'm not concerned with power consumption.

 

[STOne-32]

Dear @1f333 ,

It is the same principle for Others PLL architectures including the STM32WB55 where PLL input max is up to 16MHz, just be sure to be in specifications for the Minimum VCO output . In general for RF MCUs , Long term jitter is sensitive on top of cycle-2-cycle and period jitter.  Having the right 32MHz crystal with high Quality Q-factor is key.

ciao 

STOne-32

[Tesla DeLorean]

The VCO in most of these devices is running into the 100's of MHz, and is a pulse generator, ie not 50/50 duty.

The F2/F4 had a comparison frequency (fComp) in the PLL that needed to be in the 1 - 2 MHz range, which both your reference HSE/HSI and VCO need to be divider down into. The PLL then drives the VCO faster/slower to get to the desired speed.

The MCU needs a 50/50 duty clock, as things are happening during both phases, and this is why the VCO/PLL have a DIV2, DIV4, .. option to get you to a 50/50 clock from a rapid pulse.