CubeMX STM32F429 I2S Ext clock frequency parameter error?

[timistof]

Posted on October 28, 2015 at 23:27

Hi,

In my design I'm using an external 24.576 MHz oscilator as I2S clock source

Acoording to the reference manual, for 32 bit frames and MCLK output:

F

S

= I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] 

For 

Fs = 96 KHz, this gives

I2SDIV = 0, ODD = 1.

However, in the CubeMX configuration tab this shows an error:

''With this I2S Clock (24.576 MHz), the divider value(0) is too low to obtain the desired audio frequency(96.0 KHz).

The I2S Clock must be higher than (86.016 MHz).''

I don't understand where this 86.016 MHz is coming from.

Is there something happening between the external input pin and the I2S clock generator that I'm missing? Or is this a bug in CubeMX?

[waclawek.jan]

Posted on October 29, 2015 at 11:53

> For 

Fs = 96 KHz, this gives

I2SDIV = 0, ODD = 1.

Minimum I2SDIV is 2, see SPI_I2SPR.I2SDIV description in RM0090 Rev.11 Ch.28.5.9.

> I don't understand where this 86.016 MHz is coming from.

From CubeMX :)

The miminum input frequency is different (your homework to calculate), and I have no idea how could it be miscalculated to that value.

JW

[Nesrine M_O]

Posted on October 29, 2015 at 13:51

Hi tim, 

As Jan said the I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.

(86.016 MHz) is the value that should be in the I2S Clock to obtain the desired audio frequency (96.0 KHz).

-Syrine-

[waclawek.jan]

Posted on October 29, 2015 at 16:35

> (86.016 MHz) is the value that should be in the I2S Clock to obtain the desired audio frequency (96.0 KHz).

Certainly not; not with MCLK output set. The minimum frequency is for

I2SDIV=2, ODD=0, I2SxCLK = Fs * [(32*2)*((2*I2SDIV)+ODD)*4)]

= 96k * (32 * 2) * 2 * 2 + 0) * 4 = 98.304MHz.

Without MCLK, there *may* be one setting where 86.016MHz leads to 96kHz output, but it's not the lowest input frequency either.

JW

[timistof]

Posted on October 29, 2015 at 17:38

Right, I totally missed the forbidden values.. Derp.

Well that's too bad.. An external oscillator running at 98.304MHz is quite expensive.

I wish it would be easier to achieve error-free sampling rates.

Thanks for the insight!

[waclawek.jan]

Posted on October 29, 2015 at 18:18

> Well that's too bad.. An external oscillator running at 98.304MHz is quite expensive.

Isn't this the reason why I2S has its own PLL?

Some codecs have it too.

> I wish it would be easier to achieve error-free sampling rates.

Do you have some clocking requirement which prevents you to use the

24.576

MHz oscillator (or, better, half of that) as the main clock source?

JW

[timistof]

Posted on October 29, 2015 at 23:55

> Do you have some clocking requirement which prevents you to use the 

24.576

MHz oscillator (or, better, half of that) as the main clock source?

Yeah I thought of that too, if I use a 12.288 MHz oscilator as main clock with m=8, I can use the I2SPLL to get the 98.304 MHz I2S clock (N=128, Q =2).

I've noticed that the SAI-blocks are a bit more flexible in their clock generation than I2S, with SAI it seems I can even get Fs = 192 KHz with MCLK = 128 x Fs (that's what my ADC & DAC need at that samplerate, for others they take 256 x Fs).

The main clock would then be 179,712 MHz with main PLL N=234, P=2.

But, for accurate 44.1 KHz and their sibling sample rates, I would need a 11.2896 MHz oscilator. I can enable them seperately with GPIO's, but then I'd need to switch over to the internal 16 Mhz HSI during the changing of oscillators. So:

-Disable SAI

-Disable PLLSAI

-Set clock mux to HSI

-Disable Main PLL

-Disable external oscillator 1 (12.288 MHz)

-Enable external oscillator 2 (11.2896 MHz)

-Setup Main PLL to almost 180 MHz

-Re-enable Main PLL

-Set clock mux to PLLCLK

-Re-enable PLLSAI with N=128, R =4

-Re-nable SAI

Does this seem at all feasible or in any way possible? When setting the clock mux to HSI in CubeMX, it says that HCLK must be at least 30 MHz. So why offer this possibility?

The reason I'm contemplating this complex setup is because I would really like to use the ADC and DAC I've planned, without any samplerate error.

Cheers,

Tim

[timistof]

Posted on October 30, 2015 at 00:38

Ah, no, actually I can just use the 11.2896 MHz oscillator on the I2S external clock input and switch the SAI clock mux whenever I need to have 44.1 kHz or divide it further. 

I also see that MCLK = 256 x Fs always, but I can divide it by 2 in hardware externally to obtain MCLK = 128 x Fs for 192 kHz.

[waclawek.jan]

Posted on October 30, 2015 at 11:15

In this case, I'd consider using a CODEC with built-in fractional-N PLL or other way of generating all the needed frequencies/signals, and use that as the I2S clock source.

JW

[waclawek.jan]

Posted on October 30, 2015 at 12:02

Also, MCLK can be generated using a timer, if the AHB->APB frequency is adequate, and given the phase shift can be handled.

Also, the I2S

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/F2F4%20I2S%20Ext.Clock&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=428

- if you are in the 1Mpcs/yr cathegory, you might try to get a confirmation from ST for this.

JW

[waclawek.jan]

I know it's almost a decade old thread.

My colleague today played with I2S in CubeMX with a 'F427, set 12.288MHz at the dedicated I2S_CLK pin, and with an attempted setting of 192kHz sampling frequency it wrote something about the divider (which it calculated to be 0, fair enough) is not good, and at least 43.008MHz is required.

That's an oddly specific, yet very strange value.

I faintly remembered I've already seen something along these lines - and lo and behold, found this thread, exactly twice that value, 84.016MHz.

CubeMX was updated today (with several "funny" stories related to surprising changes in controls and behaviour).

We don't really care (more precisely, we really don't care) at this point; just mentioned it as just another fun fact.

JW