Hi,
To conclude: the DAC CAN NOT be clocked by PLL2R (silicon bug).
If, reader, like me, you want to have a "fast" ADC running in same time with DAC, you must set the analog clock switch "ADCDACSEL" to "rcc_hclk" (=SYSCLK), otherwise the DAC is not reliable. And, if, like me, you want a specific sampling frequency ("FS"), but you prefer ADC and DAC to be synchronized (for simplified signal processing), then below are some options:
1) Simpler solution. Configure the ADC in "continuous mode"; the prescaler for ADC gives few (one?) possible FS: with SYSCLK=250MHz, FS can be set to 250/4/15=4.167MHz (The "15" comes from SMP+RES=2.5+12.5 at 12 bit; the "4" is the ADC prescaler from SYSCLK). Furthermore, if you accept a light reduction of CPU power, you may tune PLL1 so that SYSCLK is lightly smaller. For instance, if you target 4.0MHz for FS, you can set SYSCLK=4*15*4=240MHz. For the DAC, a timer, for instance TIM7, must be used. Clocked by SYSCLK, it is perfectly synchronized by DAC (but phase is not controlled). Even if FS can be tweaked by sampling duration (SMP=2.5 by default, but can be set to 6.5, for instance), flexibility for FS is pretty poor. For that reason, the next option is proposed.
2) Run the ADC in "triggered mode" (clocked by, e.g. SYSCLK/4, but triggered by another source); using a low power timer (LPTIMER), and assuming PLL3 is not used for something else (like USB), it is possible to exploit the PLL3 and hence have the maximum flexibility for FS. If the DAC runs at FS too, the LPTIMER trigger can be shared for a perfectly synchronized ADC/DAC couple. If the DAC runs slower, because, for instance, ADC OVERSAMPLING is in use, you must use two different LPTIMERs since one timer can not output two different periods. Nevertheless, even if the two LPTIMERs are clocked by the same PLL3, and hence are synchronized, they might be started with a random delay (depending on the software execution time), so the phase between ADC and DAC is not controlled (neither reproductible?). For that reason, the next option is proposed.
3) Still run the ADC in "triggered mode" and use one (or two) general purpose timer(s) (GP TIMER); these timers can not be clocked by PLL2 or PLL3, unfortunately. But, even if they are clocked by the SYSCLK (maximum available speed), the FS is more flexible than in 1) because frequency dividing number being higher, there are more possibilities; and if we accept to loose some CPU power, flexibility is almost full. Example: FS=3MHz; 250/3=83.33; so the chosen period count for the GP TIMER is 83; due to that, SYSCLK must be set to 249MHz, loosing a little bit of possible CPU power.
Only one timer is needed if ADC and DAC run at same FS; in case of OVERSAMPLING is actived in the ADC, so DAC runs slower, two different timers are needed (GP TIMERs have several channels, but these channels must run with same periods). A master/slave configuration, in which clock of second GP TIMER comes from output of first one, provides a perfect synchronisation and controlled phase between ADC and DAC. Example: use TIM3 for ADC; TIM4 for DAC; ADC works in triggered mode (clocked by SYSCLK/4 but triggered by TIM3_TRGO), with OVERSAMPLING of X; TIM3 is configured for FS; optionally, one can tweak rising and falling edges for a complete sampling control (limited to by GP TIMER granularity, 1/SYSCLK, but better than SMP register); TIM4 is configured as slave of TIM3, with a period count equal to X; the rising edge can be adjusted according to required ADC/DAC phase (with 1/X of granularity; if higher granularity is required, you may use the master/slave configuration only for starting TIM4 and hence have the 1/SYSCLK granularity); eventually, DAC is configured to be triggered by TIM4 TRGO.
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I did not find any better trade-offs. But, for sure, you have a better idea for your specific use-case ;)
