DCMI affected due to enable the ICache and DCache in stm32h743

[saikumar]

Hello,

I am using the STM32H743ZI2 controller with Cortex-M7 and firmware version 1.11.2 for a project where I am capturing camera data through DCMI and sending it over Ethernet using UDP to software that receives the data and builds a video stream.

However, I am facing an issue related to cache usage:

When I enable SCB_EnableICache() and SCB_EnableDCache(), the DCMI data is not being copied into the another buffer, resulting in the data being sent over Ethernet as zeros (00000000...).  And the DCMI stops immediately capturing data.

example :---

 while(HAL_DCMI_Start_DMA(&hdcmi,DCMI_MODE_CONTINUOUS(uint32_t)&Rx_B(uint32_t)320)!=HAL_OK){}

I Have Started the the dcmi and enter into while

while(1)

{

for(int i=0 ; i<1280 ; i++){

dcmi_temp[i] = Rx_B[i];

}

}

 

When I disable the I and D cache, the DCMI data is successfully copied into the another buffer, and the data is transmitted correctly. However, the Ethernet packet sending speed drops to 30-40 Mbps.(basically speed would be in 80 - 90 Mbps).

Could anyone provide insights on why the cache affects the DCMI data transfer and how to resolve this while maintaining higher Ethernet throughput?

i have uploaded EXAMPLE code in text document . plz  check it and help me on this

Thank you in advance for your help!

[KDJEM.1]

Hello @saikumar ,

 

I think the cache issue, which you are encountering, is related to memory layout on STM32H7 and internal data cache (D-Cache) of the Cortex-M7 core.  So, when working with DMA for STM32H7 devices, you should pay attention to the memory allocation. For that could you please take a look at this FAQ and precisely at proposal solutions 

When working with DMA for STM32H7 devices, you should pay attention to the memory allocation. For more information please refer to AN4839. This application note describes the level 1 cache behavior and gives an example showing how to ensure data coherency in the STM32F7 Series and STM32H7 Series when using the L1-cache.

Please let me know if the issue is solved or not?

 

Thank you.

Kaouthar

[saikumar]

Hello,

I followed the suggestions provided, but unfortunately, the issue persists. There has been no change in the behavior, and the problem remains unsolved.

I would appreciate it if you could verify the issue with firmware version 1.11.2 and provide a fix for the bug. Please let me know once it has been resolved.  

Thank you for your cooperation.

 

 

[KDJEM.1]

Hi @saikumar ,

 

Thank you for updating post and for coming back to the community.

Did you try @STea's suggestion? Is your issue solved?

Are you able to make DCMI work perfectly without Ethernet?

Could you please take a look at this  DCMI_CaptureMode example may help you.

 

Thank you.

Kaouthar

[STea]

Hello @saikumar ,

Adding on what my colleague said you need to add the following in the MPU configuration to prevent speculative access:

void MPU_Config(void)
{
 MPU_Region_InitTypeDef MPU_InitStruct = {0};

 /* Disables the MPU */
 HAL_MPU_Disable();

 /** Initializes and configures the Region and the memory to be protected
 */
 MPU_InitStruct.Enable = MPU_REGION_ENABLE;
 MPU_InitStruct.Number = MPU_REGION_NUMBER0;
 MPU_InitStruct.BaseAddress = 0x0;
 MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
 MPU_InitStruct.SubRegionDisable = 0x87;
 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
 MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
 MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;

 HAL_MPU_ConfigRegion(&MPU_InitStruct);

 /** Initializes and configures the Region and the memory to be protected
 */
 the rest stays as is 

 HAL_MPU_ConfigRegion(&MPU_InitStruct);
 /* Enables the MPU */
 HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);

}

Please refer to the AN4861 "LCD-TFT display controller (LTDC) on STM32 MCUs" / Section 5.6 Special recommendations for Cortex-M7 (STM32F7/H7),AN4838 section 3.4 Cortex-M7 constraint speculative prefetch.

Regards