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J
JIN3473
Visitor II
August 23, 2024
Question

Display output does not appear when the start address is in SDRAM

  • August 23, 2024
  • 2 replies
  • 773 views

I conducted an experiment with the following settings and results:

  • LTDC - 0x20020000 (Internal RAM), Display - 0x20020000 (SDRAM): Display output is visible.
  • LTDC - 0xC0000000 (SDRAM), Display - 0xC0000000 (SDRAM): No display output.
  • LTDC - 0xC0000000 (SDRAM), Display - 0x20020000 (Internal RAM): Display output is visible.
  • LTDC - 0x20020000 (Internal RAM), Display - 0xC0000000 (SDRAM): Display is corrupted.

The results are puzzling because when the Display Start Address is set to SDRAM, the display output is not functioning correctly. I suspect there might be an issue with the SDRAM, but I’m confused by the fact that when LTDC is set to 0xC0000000 (SDRAM) and Display is set to 0x20020000 (Internal RAM), the display works without issues.

 

Additionally, after debugging and inspecting the memory, I can see the values written to the internal RAM, but I cannot see any values written to the SDRAM.

JIN3473_0-1724390197920.png

JIN3473_1-1724390339786.png

 

The SDRAM model I am using is the MT48LC4M32B2B5-6A_IT. I will attach an image showing the parameters I set in CubeMX.

JIN3473_2-1724390597402.png

JIN3473_4-1724390919734.png

To provide some details, the system clock is set to 216MHz, and the data width is 8 bits because the environment only supports an 8-bit configuration. The CAS Latency is set to the maximum performance of the SDRAM, and the SDRAM common clock is set to 2, resulting in 216/2 = 108MHz, which I intended to ensure would not cause issues.

At 108MHz -> 9.26ns

  • tMRD = 12ns / 9.26ns = 1.29 -> 2 clock cycles
  • tXSR = tRFC + tRP = 78ns / 9.26ns = 8.42 -> 9 clock cycles
  • tRAS = 42ns / 9.26ns = 4.54 -> 5 clock cycles
  • tRC = 60ns / 9.26ns = 6.48 -> 7 clock cycles
  • tWR = 12ns / 9.26ns = 1.3 -> 2 clock cycles
  • tRP = 18ns / 9.26ns = 1.94 -> 2 clock cycles
  • tRCD = 18ns / 9.26ns = 1.94 -> 2 clock cycles

I have configured the settings accordingly.

I would appreciate your assistance in resolving the issue.

 

    This topic has been closed for replies.

    2 replies

    M
    mƎALLEm
    Technical Moderator
    August 23, 2024

    Hello,

    You didn't mention which part number you are using. Please review tips on how to post in the community: https://community.st.com/t5/community-guidelines/how-to-write-your-question-to-maximize-your-chances-to-find-a/ta-p/575228

    For your SDRAM configuration, this article may help you: https://community.st.com/t5/stm32-mcus/how-to-set-up-the-fmc-peripheral-to-interface-with-the-sdram/ta-p/49457

      J
      JIN3473Author
      Visitor II
      August 25, 2024

      I apologize for the confusion. I am currently using the STM32F746 chip and the SDRAM MT48LC4M32B2B5-6A_IT. My development environment is STM32CubeIDE.

      I have referred to this link to configure the SDRAM, but I am encountering issues and would appreciate your assistance.

      this link : https://community.st.com/t5/stm32-mcus/how-to-set-up-the-fmc-peripheral-to-interface-with-the-sdram/ta-p/49457

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