DMA error when SRAM1 mapped at 0x00 address space in STM32L4

[IIvan.22]

When SRAM1 is remapped at 0x00000000 address space using SYSCFG_MEMRMP register, SRAM1 cannot be accessed by DMA by its remapped zero-based address. DMA error occurs at the very first transfer and DMA channel becomes disabled.

Steps to reproduce:

1. Use SYSCFG memory remap register (SYSCFG_MEMRMP) to map SRAM1 at 0x00000000.

Write 0x03 to SYSCFG_MEMRMP register.
Bits 2:0 MEM_MODE[2:0]: Memory mapping selection: 011: SRAM1 mapped at 0x00000000.

2. Use DMA to access SRAM1 using 0x00000000 as SRAM1 base address:

// to access SRAM1 at 0x20000400:
DMA1_Channel1->CMAR = 0x400;

// DMA1_Channel1->CPAR can be pointing onto ADC, SPI, etc data register.
// DMA error occures at the first transfer.

Background

SRAM1 usually remapped to zero address space for higher performance. Less instructions required to access data and run code. LD script is normally used to tell linker about this relocation. But then all data pointers generated by linker are also become remapped to the new space and hence cannot be passed directly to the DMA without re-adjustment, which now has to be aware about re-mapping too.

MCU: STM32L496

 

[Sarra.S]

Hello @IIvan.22, 

I think the issue is that the CPU may access the remapped SRAM1 correctly, but the DMA controller still uses the original physical addresses 

Also, check this related thread: https://community.st.com/t5/stm32-mcus-products/dma2-and-syscfg-memrmp-relationship/td-p/471387

[IIvan.22]

Hello Sarra,

Yes, you are right. DMA can only use the original physical address, but cannot access the re-mapped address. I believe that it is a defect: the entire point of remapping was to increase the performance, but now we have to check and re-calculate addresses in our application code. Also would be nice to mention it in the documentation, as the reason for the DMA error is not obvious.

[Sarra.S]

Hello @IIvan.22, 

This can be understood by looking at the system architecture for STM32L49x/L4Ax

When SRAM1 is remapped to zero-based address, the CPU can access the external memory via ICode bus instead of System bus which boosts up the performance, as you can see, DMA controllers cannot access the Icode bus. 

If you're looking for high performance, L4 is not the optimum choice as it's dedicated for low power applications