DMA Transfer Complete Flag strange behavior
Hi,
I am using 3 DMA channels of DMA1 on a STM32G4* to transfer data from the 3 ADCs to mem. At a certain point I want to make sure that all transfers are done and enter a while loop:
uint32_t timeoutCnt = 0;
while(!LL_DMA_IsActiveFlag_TC1(DMA1) || !LL_DMA_IsActiveFlag_TC2(DMA1) || !LL_DMA_IsActiveFlag_TC3(DMA1))
{
if( ++timeoutCnt > 400 ) // 3 load-and-compare operations per cycle -> roughly guessed 70ns; wait for max 28µs
{
// error handling
}
}
LL_DMA_ClearFlag_TC1(DMA1);
LL_DMA_ClearFlag_TC2(DMA1);
LL_DMA_ClearFlag_TC3(DMA1);
// go on with work...
Usually the DMAs should be done when execution gets here and in rare cases it may take some 100s of ns to complete.
This works most of the time. Sometimes the while loops gets stuck, that is one of the TC flags never gets set. There is no straight forward way to trigger the failure. Some software builds seem more susceptible and some hardware boards are more prone to show the error. Most builds and most boards are totally imune and run for days (>>10^9 passes) without problem. This indicates, that some subtle timing problem may be involved. (SW build moves the code around and different HW means that the timing of external interrupts and xtal frequency is slightly different.)
I can think of 2 reasons:
- Some other event clears the TC bit before I do my test. As mentioned, in most cases the DMAs are long completed when I check them, so there would be ample time for "something else" to clear them. I just have no idea what "something else" could be.
- The fast polling of the TC flag (and the bus traffic on AHB1 resulting from this polling) stalls the DMA transfer and actually keeps the TC from becoming set. Some sort of bus deadlock. But ADC is on AHB2 and the bus matrix uses a Round Robin arbitration, so I see no reason why the DMA should become stuck.
Any ideas or hints woud be highly appreciated!
Update: I am aware of the global clear bit (CGIFx) in DMA_IFCR - and I am very sure, that I never use this bit on DMAs in my code.