Hi OOUAD,
Thanks for answering! I've thought of your suggestion, but the problem is that the CCR1 (configured for rising edge) will capture the period correctly, while the CCR2 (configured for falling edge) will capture the period between the two falling edges, not the duty cycle. I understand that doing a subtraction and then writing the result through DMA does not cost much in execution time, but I'm currently working on decreasing the time needed to update the HRTIM output on-the-fly.
I would really appreciate, though, if you could give me your opinion on a "hackerish" solution I worked around (although it really depends on someones needs). After I understood that i can access the CCR2 through CCR1 with DMA Burst mode (since they are mapped one next to each other) I tried to find a similar way to write the PERxR and CMP1xR registers of HRTIM. Unfortunately, they are apart by the REPxR register and it really troubled me how to read from two 32bit addresses (in burst mode) and write (two ideally but actually) three 32bit address.
So my solution is the following, since most of the G4's timers are 16 bit I am interesting making this work correctly; Instead of accessing the TIM peripheral memory by 32bits, why don't I access it by 16bits, while for the HRTIM I can still access the memory mapped regions by 32bits?
By doing three accesses after all (CCR1, Zeros since register doesn't use them, CCR2) i can write the PERxR, REPxR and CMP1xR respectfully (And that works for me because i have no interest in using the REPxR). Now for the part that it actually runs faster that the initial one you suggested, I have to take measurement and actually find out if it is better and by how much. I think, though, that is actually a much better way, because for my next step I have to run almost all TIMs and HRTIMs simultaneously as also support serial communication etc.
I'm looking forward for your response! Feel free to let me know if I am not explaining anything as I should or I am missing something critical.
CK.