Does the STM32H7 FDCAN peripheral message RAM support ECC?

[mcole]

We're working on a new design using the STM32H753, partly based on the fact the memories have ECC implemented, but the documentation does not mention what technology is used for the FDCAN message RAM.

Can someone elaborate on what protections exist for data integrity between CRC validation and a read from message RAM?

Likewise, is there any protection against or indication of memory faults for any other features supported by message RAM?

[mƎALLEm]

Hello @mcole and welcome to the community,

 

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@mcole wrote:

We're working on a new design using the STM32H753, partly based on the fact the memories have ECC implemented, but the documentation does not mention what technology is used for the FDCAN message RAM.

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All internal H7 SRAMs feature Error Correction Code (ECC) except the RAM dedicated to FDCAN.

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Can someone elaborate on what protections exist for data integrity between CRC validation and a read from message RAM?

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CRC is part of the protocol and the peripheral implementation. The FDCAN RAM is a part of the SoC integration. As said, there is no ECC for this RAM and there is no other data integrity mechanism in the path from the peripheral to the message RAM.

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Likewise, is there any protection against or indication of memory faults for any other features supported by message RAM?

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Only in the other RAMs when you read the message from the FDCAN RAM. So you can detect ECC errors when it occurs in these memories.

Hope I answered your questions.

[mcole]

Thank you, yes. This confirms my assumptions