DSI issues driving a SN65DSI86

[balint]

Dear forum mmebers,

I am trying to use an STM32U5G9 MCU to drive a Ti SN65DSI86 DSI to eDP converter with no success.

Previously I have evaluated the SN65DSI86 with a Xilinx FPGA as a DSI source where it was working perfectly from 640x480 to 1920x1200 resolution at 60Hz refresh rate. The line rate was up to 900Mbps/lane. At 640x480@60Hz I used 2 lanes and 250Mbps/lane. The SN65DSI86 can be configured to output the VSYNC on one of its GPIO which can be used to verify that DSI data is at least partially correct.
I have also succesfully evaluated the STM32U5G9J-DK1 evaluation board with its display (round, 480x480) so both the STM32U5G9 and Ti SN65DSI86 works.

Now we have manufactured an extension board for the STM32U5G9J-DK1 which has the Ti SN65DSI86 and a DisplayPort connector to drive a monitor. I am trying to use 640x480@60Hz and the STM32's internal test pattern generator in the DSI. Now I can see that the 60Hz VSYNC signal is present on the SN65DSI86 but it gives no picture at all.
What I can not understand if the VSYNC signal is present in the SN65DSI86 DSI receiver why the image is not transmitted to the monitor.
Do somebody have an idea whether I had configured something wrong? (Attached the DSI config.)

[balint]

One more thing: The Ti SN65DSI86 also have a HSYNC output. I've put an oscilloscope on it and I've seen that there is HSYNC in the vertical back porch area but nothing after that nor in the active area neither in the front porch. The next VSYNC is fine and the HSYNC pattern is also fine until the end if the back porch. I use non burst mode with events.

[mathiasmarkussen]

Have you tried to enable the DSI interrupt for debugging?

You should be able to inspect the DSI host handle and see if it's in an error state.

Would you mind sharing s screenshots of the configuration in CubeMX?

[balint]

Dear Mathias!

I've enabled DSI error interrupts but there is no error.

I've configured the SN65DSI86 DSI receiver to output both the VSYNC and HSYNC on its GPIOs. I can see all VSYNC signals but the HSYNC stops at the beginning of the active area of each line.
On the oscilloscope I can see 36 HSYNC pulse after a VSYNC pulse. The vertical sync width is 2 lines and the vertical back porch is 33 lines so I assume the HSYNC stops after the first line in the active region.

The SN65DSI86 shows two errors:
- CHA_DATATYPE_ERR: When the DSI channel A packet processor detects a unrecognized DSI data.
- LOSS_OF_DP_SYNC_LOCK_ERR: This field is set whenever the DP sync generator has lost lock with the DSI sync stream.
However I guess the LOSS_OF_DP_SYNC_LOCK_ERR is a consequence of the first error.

I've attached the screenshots from CubeMX. However I had to modify one thing manually: On the Display Interface tab the Number of chunks is incorrect: It should be 4 I guess since the video packet size x number of packets = number of pixels per line. (160x4=640)

Thank you for your help!

[mathiasmarkussen]

What version of CubeMX are you using?

Can you share your LTDC configuration as well?

For me, using CubeMX 6.14, the number of chunks is calculated correctly in the UI as shown in my screen shot. I could definitely imagine getting problems (especially related to timing) if the any parameter is set up to support 25600 pixels per line (160*160 as shown in your screen shot), but is only set up to deliver to 640.