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YRakh.1
Graduate
May 30, 2024
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Dual CAN STM32F105

  • May 30, 2024
  • 2 replies
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To implement a "bridge" devise between two independent CAN buses, the STM32F105R8 chip was chosen. From the specifications it follows that it has 2 CAN buses, but going deeper into it I realized that they share a lot of resources among themselves.

could you help me clarify the following:

1. can this chip, from a software/hardware point of view, support 2 CAN buses operating at different speeds CAN1=250kbps and CAN2=500kbps for example?

2. the delay in sending messages from CAN1 to CAN2 is critical for this device, could someone let me know if problems can arise with this?

3. are there any restrictions on the maximum number of TX/RX messages (CAN_IDs) for two buses? As far as I understand, CAN filters are shared to CAN1 and CAN2...

 

Thanks in advance everyone for your help!

    This topic has been closed for replies.
    Best answer by mƎALLEm

    Hello,

    These are my comments:

    1. can this chip, from a software/hardware point of view, support 2 CAN buses operating at different speeds CAN1=250kbps and CAN2=500kbps for example?

    Yes. CAN1 and CAN2 are independent from this standpoint.

    2. the delay in sending messages from CAN1 to CAN2 is critical for this device, could someone let me know if problems can arise with this?

     

    It depends on the number of messages handled at a time and how the CPU can manage it. I think you need to handle Rx/Tx message with a ring buffer.

    3. are there any restrictions on the maximum number of TX/RX messages (CAN_IDs) for two buses? As far as I understand, CAN filters are shared to CAN1 and CAN2...

     

    Each CAN instance has:

    • RX 2xFIFOs, Each FIFO can accept 3 messages. So each CAN instance can accept 6 Rx message in total.
    • TX: 3 mailboxes. The filter resources depend on the amount of filters you're using at both sides. Logically, in your case, you need the same amount of filters. So Start Bank = 14 (CANSB[5:0] in CAN_FMR register) 

    Hope I answered your questions.

    2 replies

    M
    mƎALLEmAnswer
    Technical Moderator
    June 5, 2024

    Hello,

    These are my comments:

    1. can this chip, from a software/hardware point of view, support 2 CAN buses operating at different speeds CAN1=250kbps and CAN2=500kbps for example?

    Yes. CAN1 and CAN2 are independent from this standpoint.

    2. the delay in sending messages from CAN1 to CAN2 is critical for this device, could someone let me know if problems can arise with this?

     

    It depends on the number of messages handled at a time and how the CPU can manage it. I think you need to handle Rx/Tx message with a ring buffer.

    3. are there any restrictions on the maximum number of TX/RX messages (CAN_IDs) for two buses? As far as I understand, CAN filters are shared to CAN1 and CAN2...

     

    Each CAN instance has:

    • RX 2xFIFOs, Each FIFO can accept 3 messages. So each CAN instance can accept 6 Rx message in total.
    • TX: 3 mailboxes. The filter resources depend on the amount of filters you're using at both sides. Logically, in your case, you need the same amount of filters. So Start Bank = 14 (CANSB[5:0] in CAN_FMR register) 

    Hope I answered your questions.

      K
      Karl Yamashita
      Graduate II
      June 5, 2024

      I've used an STM32F105 as a bridge without using filters. So all CAN messages were received on CAN1 and CAN2. They would pass messages through from CAN1 to CAN2 and CAN2 to CAN1, except for the ones I was interested in. For those messages I just modify the CAN data and then pass the modified message through. I used a IntrepidCS neoVI Fire 2 to monitor the messages on both sides of the bridge. Not one message was missed being passed through. 

       

      I did use a ring buffer for both Rx and Tx messages. Depending on what you do in the CAN interrupt, can make or break your project. I'm in and out of the interrupt using an efficient ring buffer. That is why i don't miss any CAN messages even using 1 CAN Rx Fifo. I was pleasantly surprised how well the STM32F105 could handle the CAN messages efficiently without CAN ID filters. 

       

      One of the several things i did was intercept the vehicle gear information while the vehicle was being driven but tricked the Radio into thinking the vehicle was in reverse. This would enable the rear camera input so we could feed in an outside video source. 

        T
        Tesla DeLorean
        Graduate II
        June 5, 2024

        As I recall most of the commonality between the cores was the parallel pattern matching circuit for the filters. Took up a lot of gates, and ran very fast.

        Not sure if it was CAM (content address-able memory), but it definitely wasn't a sequential look-up-compare design.

        Each had it's own FIFO, and transmission buffers.

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