DUTY-CYCLE of QUADSPI CLK changed to 25% after 4GB indirect read

[primetime]

Hi ST team,

I'm using STM32H743IIT6 with REV_ID=0x2003 and encountered a problem. Quadspi dual-flash indirect read mode is used for continuous reading data from external. According to RM0433, If QUADSPI_DLR = 0xFFFF_FFFF and FSIZE = 0x1F (max value indicating a 4-Gbyte flash memory), then in this special case, transfers continue indefinitely.

 

But I found that after the 1st 4GB is transferred, the frequency of QUADSPI CLK pin dropped to it half value, for example from 2MHz to 1MHz, without any error indicator. After that, the 2nd, 3rd and so on, 4GB transfer will remain 1MHz clock operation continuously. Meanwhile, the duty cycle of CLK is changed to 25%, as follows: 

 

 

 

 

I read configuration registers of PRESCALER in QUADSPI_CR and other clock configuration registers after clock frequency dropped, they are not be changed. And the patch of 2.7.4 "QUADSPI internal timing criticality" in ERRATA_DATASHEET has been added.

 

Our congfiguration of QUADSPI is list below:

CR = 0x4f010f45
DCR = 0x1f0000
SR = 0x0222
FCR = 0x0000
DLR = 0xffffffff
CCR = 0x96103800
AR = 0x0000
ABR = 0x0000

I also tried single-flash mode, the clock is stopped after 1st 4GB is transferred, just like the below thread :

QuadSPI hangs with BUSY after 4 GB indirect read - STMicroelectronics Community

after clock is stopped, the QUADSPI_SR=0x0022, means FIFO is empty but busy=1. 

Is there any workaround scheme?

Thanks.

[primetime]

We just found that the time of frequency change is related to QSPI_AR, when QSPI_AR=0xFFFFFFFE，only 14 cycles of 2MHz CLK is transferred, than it is changed to 1M which duty-cycle of 25%:

 

14 cycle = 8 cycle address + 4 cycle dummy + 2cycle data

[primetime]

in SDR mode, after 4GB transfer, the clock will lack 1 cycle in every 4cycles: