Skip to main content
Visitor II
November 9, 2020
Question

ESP-PSRAM64H and STM32H743 QSPI mode

  • November 9, 2020
  • 14 replies
  • 8663 views

Hi,

Is there any one success with ESP-PSRAM64H in memory mapped mode?

We are able to read ID (0x9F) in spi mode. But when we read/write, it return 0xFF. We don't see EnableWrite command, does this chip has EnableWrite command?

We also wanted to use this memory as RAM so we can read and write from a pointer.

But how we send Read and Write command Id at the same time when set register at memory mapped mode?

Many thanks

    This topic has been closed for replies.

    14 replies

    Explorer
    December 8, 2020

    Hi,

    The QuadSPI memory Controller of the STM32H743 is a NOR memory Controller and so it doesn't support Memory Mapped Write function

    Other version of STM32H7 (for example H7A3/B3/B0 or H72x/73x) does support full functionality of of QSPI or OPI RAM

    Alex

    By the way, the ESP-PSRAM64H is only supporting ESP32, equivalent Quad RAM PN to use is APS6404L-3SQR-SN (16Mb or other package also available)

    Visitor II
    September 13, 2024

    I'm looking for a processor beyond the H743 that can support Memory Mapped Write function to a QSPI SRAM or possibly a 12 pin PSRAM of at least 32Mbits.   I'm having trouble confirming that the FMC can support the 12 pin PSRAM in HyperBus (see Infineon S27KL0642DPBHI020).

    Will the FMC Memory Mapped Read and Writes respect the HyperBus RDWS line and the needed command interface? 

    From CubeMX with the H743, the FMC signals are CLK, NOE, NWE, NWAIT, NL, NE1, plus the 8 data lines.  If there is any hope of this working, it appears the NWAIT would need an inverted sense of RDWS from the PSRAM.


    If the choice is another processor, I need the 2MB Flash, 1MB RAM, Ethernet MAC, along with a UART.  To fit on my PWB, I need a BGA100 at 0.8mm pitch.  It looks like the H7Ax/Bx you mentioned above are missing the Ethernet MAC.

    Any suggestions?

    Explorer II
    January 8, 2021

    If you only want to read and write, you can use a STM32H743:

    Using an ESP-PSRAM64H with a STM32H743:

    https://github.com/koendv/micropython-psram

    If you want to do memory-mapping, you need a STM32H7A3:

    https://github.com/koendv/micropython-spiram

    but I am still working on that.

    Explorer
    January 8, 2021

    Hi,

    If you don't need the Memory Mapped Write mode, you can use the NOR Memory controller of STM32H743 to drive the Quad PSRAM (this is not officially supported/tested by STM, formally support NOR not RAM, but we have multiple customer using it for Quad PSRAM). Please note ESP-PSRAM64H is only valid to be used in combination of ESP32, so you should use APS6404L-3SQR-SN.

    Yes for the full Quad (APSxx04x-xSQR-xx) or Octal (APSxx08x-xOBx-xx) PSRAM support, you can use the latest version of STM32 series such as  STM32L5, STM32L4P5/Q5, STM32H7A3/B3, STM32H72x/3x. If you are looking for reference, the STM32L4P5G-DK has both QSPI and OPI PSRAM foot print on board (https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-mpu-eval-tools/stm32-mcu-mpu-eval-tools/stm32-discovery-kits/stm32l4p5g-dk.html)

    Alex

    Explorer II
    January 24, 2021

    I am afraid reading the errata is fruitful on this one.

    After experimenting with a single 64Mbit qspi psram on stm32h7a3:

    • reading and writing in spi and qspi mode using HAL_OSPI_Command(), HAL_OSPI_Receive(), HAL_OSPI_Transmit() works fine.
    • when memory mapping the spi ram using HAL_OSPI_MemoryMapped(), even though the spi ram does not have a DQS pin, set HAL_OSPI_DQS_ENABLE during write, HAL_OSPI_DQS_DISABLE during read; else hardfault during write. Described in errata "Memory-mapped write error response when DQS output is disabled.
    • when memory mapping the spi ram, setting MPU_TEX_LEVEL1, MPU_ACCESS_CACHEABLE, MPU_ACCESS_BUFFERABLE results in occasional data corruption during write.

    Terminal ready
    spiram eid 0d 5d 52 a2 64 31 91 31
    spiram memtest16 fail, address 0x903e2070 written 0x5a5a read 0x0000
    MicroPython v1.13-260-g0b108aaa0-dirty on 2021-01-24; DEVEBOX STM32H7XX with STM32H7A3

    If I connect a logic analyser to the qspi bus, I see the data going from processor to spi ram is occasionally corrupt: when I do a write, sometimes some bytes still have the value from before the write. This seems to be a cache issue. I'm not aware of a workaround. Correct me if I'm wrong.

    Source code used.

    Visitor II
    March 30, 2022

    Dear koendv, We have also chosed stm32h7a3 and APS6404L-3SQR. We have exactly the same problem using ospi and memory mapping in write mode. I wonder if you managed to solved the problem? If so, can you please share it with us?

    Artin

    Explorer
    March 30, 2022

    Hi Artin,

    STM32H7A3 won't support QSPI SDR RAM mapped memory write.

    But OSPI is running well, so alternative if manageable could be 64Mb OPI BGA24 3V APS6408L-3OBM-BA (or 128Mb QSPI DDR 1.8V WLCSP)

    Regards

    Alex

    Visitor II
    March 30, 2022

    Dear Alex,

    Do you mean that APS6404L-3SQR and STM32H7A3 doesn't work in OSPI/quad mode and memory mapping?

    /Artin

    Explorer
    March 30, 2022

    Hi Artin,

    Correct, it support all functions, except Memory Mapped Write in Quad SDR

    Quad DDR or OPI works full spec

    Can you deal with OPI memory device  APS6408L-3OBM-BA ?

    Regards

    Alex

    Visitor II
    March 30, 2022

    Dear Alex,

    Thanks a lot for the reply! I will try to test it with APS6408L-3OBM-BA if we have enough pins. Is there any sample code for it for our STM32H7A3VIT?

    /Artin

    Graduate II
    March 30, 2022