FDCAN STM32H753VIT6 – Unable to Achieve >1.92 Mbps Data Rate (PLL1Q = 40 MHz)

[pavanl]

Hi ST Community,

I’m working on a CAN FD project using the STM32H753VIT6 and facing a limitation with data phase bitrate while using Bit Rate Switching (BRS).

My Setup:

• Controller: STM32H753VIT6

• FDCAN clock source: PLL1Q

• PLL1Q output: 40 MHz

• Frame format: CAN FD with BRS (FDCAN_FRAME_FD_BRS)

• Nominal (arbitration) bitrate: 1 Mbps

• Target data bitrate: 2 Mbps or higher
  
  

   Problem:

  Despite the configuration, I'm not able to achieve more than ~1.92 Mbps on the data phase. Even when I reduce the number of time quanta or adjust prescalers, the speed does not increase beyond this limit.

   My Questions:

  1. Is there any known limitation when using PLL1Q = 40 MHz for FDCAN clock?

  2. Is the STM32H753 internal FDCAN limited to certain bitrates per kernel clock frequency?

  3. Could internal synchronization or sampling constraints prevent achieving the expected 2.5 Mbps from a 40 MHz FDCAN clock?

     Attachments:

     • main.c file

     • Oscilloscope screenshot showing BRS waveform and time base

     • STM32CubeMX clock configuration screenshot

  Any insights or suggestions would be greatly appreciated!
  
  Thanks in advance,
  Pavan

[mƎALLEm]

Hello,

I don't think there is a limitation 40Mhz vs bitrate > 2Mb/s

Refer to this article: STM32 FDCAN running at 8 Mb/s on NUCLEO boards on which we showed that we can reach 8Mb/s in data phase.

Check also your transceiver bandwidth.

Meanwhile refer to this article: FAQ: Fixing STM32 FDCAN communication disruptions - APB bus, kernel, and time quanta clocks and check if you are in the same situation

[pavanl]

Thank you for your response.

My transceiver bandwidth is 5 MHz for FDCAN and 1 MHz for classic CAN.

I followed the same clock configuration as mentioned, but I'm still unable to achieve a speed beyond 2 Mbps. Could you please suggest the best approach to troubleshoot this issue? If there’s a possibility of any mistake in my configuration or code, I would really appreciate your guidance.

Thanks again.

[mƎALLEm]

Were you able to achieve the target bitrate in Loopback mode?

[MHoll.2]

I think You have set the Data baudrate wrong. If You have set the FDCAN Clock to 50MHz then Your setup:

 hfdcan1.Init.NominalPrescaler = 1;
 hfdcan1.Init.NominalSyncJumpWidth = 4;
 hfdcan1.Init.NominalTimeSeg1 = 86;
 hfdcan1.Init.NominalTimeSeg2 = 13;
 hfdcan1.Init.DataPrescaler = 1;
 hfdcan1.Init.DataSyncJumpWidth = 2;
 hfdcan1.Init.DataTimeSeg1 = 10;
 hfdcan1.Init.DataTimeSeg2 = 2;

will result in:

Nominal Bitrate: 50e6/(1+86+13) = 500e3 (500kBit)

Data Bitrate: 50e6/(1+10+2) = 3.8462e6(!)

if You want 500KBit/2Mbit You have to cange the Data segment's (for example 20 and 4)

[pavanl]

i already set this with 50 MHz. but I don't get more than 1.92 mbps"

 

[mƎALLEm]

You didn't answer that question: did you try with the Loopback mode?