FMC SRAM read data sampling time

[Gael Le Moing]

Hi,

I am working with STM32H753 and I am developing baremetal application using FMC. The FMC is interfaced with an external asynchronous memory, address and data signals are not muxed and there is no need for NWAIT, NADV nor CLK signals.

On the FMC side, it refers to an SRAM configuration, and I am trying to figure out the correct configuration to optimize read and write accesses, while respecting the memory specific timings from the datasheet.

But to do that, I think the STM32 reference manual is not clear about the FMC kernel clock cycle where the incoming data is sampled for a read access: in Figure 99 of RefMan Rev7, the FMC cycle where the data is sampled by the FMC during the DATA SETUP phase (which duration is defined by the DATAST field of BTR register) is not shown. In section 22.7.4, it is stated that "The FMC always samples the data before deasserting the Chip Select signal." but does it mean "at the last cycle of data setup phase"?

Thanks

[MHAJJ]

Hi Gael,

The FMC always samples the data before deasserting the Chip Select signal, that's to make sure that the data is read before deselecting the memory which may abort outputting the data from the memory side.

The data setup time is about to give enough time for the memory to output the data on the IOs and stabilize.

Regards,

Mahmoud.

[Kurngop32]

I don't understand it either. From what I see, the data is sampled when (or until) NOE goes high. Interestingly this is not the same moment as when NEx goes high, like the figure in the manual suggests. NEx goes high one clock cycle later.

In the following example you can see a change of the data at the red cursor. this is the data that gets sampled (0xFF). NEx goes high one clock later so it should read 0x00 at this moment, but it does not.

(clkf is 12 MHz HSE input clock and also the FMC clock. on the other end is a FPGA)